MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 87

• Manufacturer Part Number: MPC8536-RDK
• Description: BOARD REF COMEXPRESS MPC8536
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536-RDK

• Contents: CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

All values refer to V
Bus free time between a STOP and START condition
Noise margin at the LOW level for each connected device
(including hysteresis)
Noise margin at the HIGH level for each connected device
(including hysteresis)
Note:
1. The symbols used for timing specifications herein follow the pattern of t
2. As a transmitter, the MPC8536E provides a delay time of at least 300 ns for the SDA signal (referred to the Vihmin of the SCL
3. The maximum t
4. C
Figure 51
Figure 52
Freescale Semiconductor
for inputs and t
(I2) with respect to the time data input signals (D) reach the valid state (V) relative to the t
high (H) state or setup time. Also, t
(S) went invalid (X) relative to the t
timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the t
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop condition.
When the MPC8536E acts as the I
load on SCL and SDA are balanced, the MPC8536E would not cause unintended generation of Start or Stop condition.
Therefore, the 300 ns SDA output delay time is not a concern. For details of the I
the I
frequency for the MPC8536E.MPC8536E
B
SDA
= capacitance of one bus line in pF.
SCL
2
C Frequency Divider Ratio for SCL (AN2919). Note that the I
provides the AC test load for the I
shows the AC timing diagram for the I
S
IH
(first two letters of functional block)(reference)(state)(signal)(state)
I2DVKH
(min) and V
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
t
I2CF
t
I2CL
t
I2SXKL
has only to be met if the device does not stretch the LOW period (t
Parameter
Output
IL
(max) levels (see
Table 64. I
I2SXKL
2
I2C
C bus master while transmitting, the MPC8536E drives both SCL and SDA. As long as the
clock reference (K) going to the low (L) state or hold time. Also, t
Figure 52. I
t
I2DXKL,
symbolizes I
2
2
C AC Electrical Specifications (continued)
C.
Figure 51. I
Table
Z
t
2
I2DVKH
0
C bus.
t
I2OVKL
= 50 Ω
63).
t
I2CH
2
C Bus AC Timing Diagram
2
C timing (I2) for the time that the data with respect to the start condition
t
I2SXKL
2
C AC Test Load
Symbol
t
I2KHDX
Sr
2
V
V
C Source Clock Frequency is half of the CCB clock
NH
NL
for outputs. For example, t
(first two letters of functional block)(signal)(state) (reference)(state)
t
I2SVKH
1
t
I2KHKL
R
L
0.1 × OV
0.2 × OV
= 50 Ω
2
C frequency calculation, refer to Determining
Min
1.3
DD
DD
t
I2PVKH
I2C
OV
I2CL
DD
t
clock reference (K) going to the
) of the SCL signal.
I2CR
Max
I2DVKH
/2
—
—
—
P
symbolizes I
I2PVKH
t
I2CF
Unit
μs
V
V
symbolizes I
S
2
C timing
I2C
Notes
—
—
—
clock
2
I
2
87
C
C