MPC8536-RDK Freescale Semiconductor, MPC8536-RDK Datasheet - Page 90

• Manufacturer Part Number: MPC8536-RDK
• Description: BOARD REF COMEXPRESS MPC8536
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536-RDK

• Contents: CSB1880, CSB1801, Cables, Documentation, Enclosure, Power Supply with cord
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI
Figure 54
Figure 55
90
HRESET high to first FRAME assertion
Rise time (20%–80%)
Failing time (20%–80%)
Notes:
1. Note that the symbols used for timing specifications herein follow the pattern of t
2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications .
3. All PCI signals are measured from OV
4. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current
5. Input timings are measured at the pin.
6. The timing parameter t
7. The setup and hold time is with respect to the rising edge of HRESET.
8. The timing parameter t
9. The reset assertion timing requirement for HRESET is 100 μs.
block)(signal)(state) (reference)(state)
example, t
relative to the SYSCLK clock, t
PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid
(V) state.
question for 3.3-V PCI signaling levels.
delivered through the component pin is less than or equal to the leakage current specification.
frequencies. The system clock period must be kept within the minimum and maximum defined ranges. For values
see
Bus Specifications .
provides the AC test load for PCI.
shows the PCI input AC timing conditions.
Section 22,
PCIVKH
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
“Clocking.”
Parameter
symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V)
Table 68. PCI AC Timing Specifications at 66 MHz (continued)
Output
Figure 55. PCI Input AC Timing Measurement Conditions
SYS
PCRHFV
Input
CLK
indicates the minimum and maximum CLK cycle times for the various specified
SYS
for inputs and t
is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI 2.2 Local
, reference (K) going to the high (H) state or setup time. Also, t
DD
Figure 54. PCI AC Test Load
/2 of the rising edge of PCI_SYNC_IN to 0.4 × OV
Z
0
t
PCIVKH
= 50 Ω
(first two letters of functional block)(reference)(state)(signal)(state)
Symbol
t
t
t
PCRHFV
PCICLK
PCICLK
1
R
Min
0.6
0.6
10
L
= 50 Ω
t
PCIXKH
(first two letters of functional
Max
OV
2.1
2.1
—
DD
/2
DD
Freescale Semiconductor
of the signal in
PCRHFV
clocks
Unit
ns
ns
for outputs. For
symbolizes
Notes
—
—
8