MPC8536BVTAUL Freescale Semiconductor, MPC8536BVTAUL Datasheet - Page 47

• Manufacturer Part Number: MPC8536BVTAUL
• Description: Microprocessors (MPU) 8536 INDUSTRIAL 1333
• Manufacturer: Freescale Semiconductor

Specifications of MPC8536BVTAUL

• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1333 MHz
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: 0 C
• Package / Case: FCPBGA-783
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

At recommended operating conditions with L/TV
GTX_CLK clock period
GTX_CLK duty cycle
GTX_CLK to TCG[9:0] delay time
GTX_CLK rise (20%–80%)
GTX_CLK fall time (80%–20%)
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
2. Data valid t
Figure 21
2.9.2.4
This section describes the TBI transmit and receive AC timing specifications.
2.9.2.4.1
Table 32
Freescale Semiconductor
for inputs and t
transmit timing (TT) with respect to the time from t
state (V) or setup time. Also, t
(H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in general, the clock reference symbol
representation is based on three letters representing the clock of a particular functional. For example, the subscript of t
represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R
(rise) or F (fall).
Hold)
provides the TBI transmit AC timing specifications.
shows the MII receive AC timing diagram.
TTKHDV
TBI AC Timing Specifications
Parameter/Condition
(first two letters of functional block)(reference)(state)(signal)(state)
TBI Transmit AC Timing Specifications
RXD[3:0]
RX_CLK
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
to GTX_CLK Min Setup time is a function of clock period and max hold time. (Min Setup = Cycle time - Max
RX_DV
RX_ER
TTKHDX
Table 32. TBI Transmit AC Timing Specifications
Figure 21. MII Receive AC Timing Diagram
t
t
symbolizes the TBI transmit timing (TT) with respect to the time from t
MRXH
MRDVKH
DD
of 3.3 V ± 5%.
t
MRX
TTX
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
(K) going high (H) until the referenced data signals (D) reach the valid
Valid Data
t
Symbol
TTXH
t
TTKHDX
t
t
TTXR
t
TTXF
TTX
/t
t
MRXF
TTX
2
1
for outputs. For example, t
(first two letters of functional block)(signal)(state )(reference)(state)
t
Min
1.0
MRDXKL
40
—
—
—
t
MRXR
Typ
8.0
—
—
—
—
TTKHDV
symbolizes the TBI
Max
5.0
1.0
1.0
60
—
TTX
(K) going high
Unit
ns
ns
ns
ns
%
TTX
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