LCMXO640C-3TN100C Lattice, LCMXO640C-3TN100C Datasheet - Page 11
![CPLD - Complex Programmable Logic Devices 640 LUTS 74 I/O](/photos/16/2/160258/tqfp-100_sml.jpg)
LCMXO640C-3TN100C
Manufacturer Part Number
LCMXO640C-3TN100C
Description
CPLD - Complex Programmable Logic Devices 640 LUTS 74 I/O
Manufacturer
Lattice
Series
MachXOr
Datasheet
1.LCMXO640C-3TN100C.pdf
(95 pages)
Specifications of LCMXO640C-3TN100C
Memory Type
SRAM
Number Of Macrocells
320
Delay Time
4.9 ns
Number Of Programmable I/os
74
Operating Supply Voltage
1.8 V, 2.5 V, 3.3 V
Supply Current
17 mA
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Package / Case
TQFP-100
Mounting Style
SMD/SMT
Supply Voltage (max)
3.465 V
Supply Voltage (min)
1.71 V
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
4.9ns
Voltage Supply - Internal
1.71 V ~ 3.465 V
Number Of Logic Elements/blocks
-
Number Of Gates
-
Number Of I /o
74
Operating Temperature
0°C ~ 85°C
Mounting Type
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO640C-3TN100C
Manufacturer:
STC
Quantity:
12 000
Company:
Part Number:
LCMXO640C-3TN100C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LCMXO640C-3TN100C
Manufacturer:
LATTICE
Quantity:
20 000
Lattice Semiconductor
Figure 2-8. Primary Clocks for MachXO1200 and MachXO2280 Devices
Four secondary clocks are generated from four 16:1 muxes as shown in Figure 2-9. Four of the secondary clock
sources come from dual function clock pins and 12 come from internal routing.
Figure 2-9. Secondary Clocks for MachXO Devices
Routing
Routing
12
Up to 9
Clock
Pads
Clock
Pads
4
4
Outputs
PLL
Up to 6
2-8
16:1
16:1
16:1
16:1
16:1
16:1
16:1
16:1
Primary Clock 0
Primary Clock 1
Primary Clock 2
Primary Clock 3
Secondary (Control)
Clocks
MachXO Family Data Sheet
Architecture