LCMXO640C-3TN100C Lattice, LCMXO640C-3TN100C Datasheet - Page 95
![CPLD - Complex Programmable Logic Devices 640 LUTS 74 I/O](/photos/16/2/160258/tqfp-100_sml.jpg)
LCMXO640C-3TN100C
Manufacturer Part Number
LCMXO640C-3TN100C
Description
CPLD - Complex Programmable Logic Devices 640 LUTS 74 I/O
Manufacturer
Lattice
Series
MachXOr
Datasheet
1.LCMXO640C-3TN100C.pdf
(95 pages)
Specifications of LCMXO640C-3TN100C
Memory Type
SRAM
Number Of Macrocells
320
Delay Time
4.9 ns
Number Of Programmable I/os
74
Operating Supply Voltage
1.8 V, 2.5 V, 3.3 V
Supply Current
17 mA
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Package / Case
TQFP-100
Mounting Style
SMD/SMT
Supply Voltage (max)
3.465 V
Supply Voltage (min)
1.71 V
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
4.9ns
Voltage Supply - Internal
1.71 V ~ 3.465 V
Number Of Logic Elements/blocks
-
Number Of Gates
-
Number Of I /o
74
Operating Temperature
0°C ~ 85°C
Mounting Type
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO640C-3TN100C
Manufacturer:
STC
Quantity:
12 000
Company:
Part Number:
LCMXO640C-3TN100C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LCMXO640C-3TN100C
Manufacturer:
LATTICE
Quantity:
20 000
www.latticesemi.com
© 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
October 2005
For Further Information
A variety of technical notes for the MachXO family are available on the Lattice web site at www.latticesemi.com.
For further information on interface standards refer to the following web sites:
• MachXO sysIO Usage Guide (TN1091)
• MachXO sysCLOCK PLL Design and Usage Guide (TN1089)
• MachXO Memory Usage Guide (TN1092)
• Power Calculations and Considerations for MachXO Devices (TN1090)
• MachXO JTAG Programming and Configuration User’s Guide (TN1086)
• Minimizing System Interruption During Configuration Using TransFR Technology (TN1087)
• MachXO Density Migration (TN1097)
• IEEE 1149.1 Boundary Scan Testability in Lattice Devices
• JEDEC Standards (LVTTL, LVCMOS): www.jedec.org
• PCI: www.pcisig.com
6-1
MachXO Family Data Sheet
Supplemental Information
Further Information_01.1
Data Sheet