AGLE600V2-FGG484 Actel, AGLE600V2-FGG484 Datasheet - Page 30

• Manufacturer Part Number: AGLE600V2-FGG484
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AGLE600V2-FGG484

• Processor Series: AGLE600
• Core: IP Core
• Maximum Operating Frequency: 526.32 MHz, 892.86 MHz
• Number Of Programmable I/os: 270
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 600 K
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IGLOOe DC and Switching Characteristics
User I/O Characteristics
Figure 2-3 • Timing Model
2- 16
Input LVTTL/LVCMOS 3.3 V
Clock
LVPECL
M-LVDS
BLVDS,
LVDS,
Timing Model
Operating Conditions: Std. Speed, Commercial Temperature Range (T
VCC = 1.425 V, Applicable to 1.5 V DC Core Voltage, V2 and V5 devices
t
PY
= 1.10 ns
t
PY
(Non-Registered)
(Registered)
I/O Module
t
I/O Module
PY
= 1.45 ns
t
t
ICLKQ
ISUD
= 1.62 ns
= 0.47 ns
= 0.43 ns
D
Q
Register Cell
t
t
CLKQ
SUD
D
= 0.82 ns
= 0.90 ns
Combinational Cell
Clock
Input LVTTL/LVCMOS 3.3 V
Q
Combinational Cell
t
PD
t
Combinational Cell
PD
= 1.77 ns
Combinational Cell
Combinational Cell
t
= 1.19 ns
PY
t
PD
t
= 1.10 ns
PD
R e visio n 8
= 0.90 ns
t
PD
= 1.33 ns
Y
= 0.85 ns
Y
Y
Y
Y
Combinational Cell
Input LVTTL/LVCMOS 3.3 V
Clock
t
PD
Register Cell
t
t
CLKQ
SUD
(Non-Registered)
D
(Non-Registered)
= 1.04 ns
(Non-Registered)
I/O Module
t
t
I/O Module
t
DP
= 0.82 ns
I/O Module
DP
DP
= 0.90 ns
t
PY
Q
= 3.30 ns
= 3.13 ns
= 2.76 ns
= 1.10 ns
Y
(Non-Registered)
J
t
DP
I/O Module
= 70°C), Worst-Case
LVTTL/LVCMOS 3.3 V
Output drive strength = 12 mA
High slew rate
LVTTL/LVCMOS 3.3 V
Output drive strength = 24 mA
High slew rate
LVCMOS 1.5V
Output drive strength = 12 mA
High slew
D
t
t
= 1.75 ns
OCLKQ
OSUD
(Registered)
I/O Module
Q
= 0.52 ns
= 1.02 ns
t
DP
= 1.85 ns
LVPECL
GTL+ 3.3V