agle600 Actel Corporation, agle600 Datasheet
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agle600 Summary of contents
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... M1 IGLOOe Devices—Cortex™-M1 Soft Processor Available with or without Debug FG256, FG484 for more information. IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation I/O Standards: LVTTL, LVCMOS ® e Family Phase Shift, Multiply/Divide, AGLE600 AGLE3000 M1AGLE3000 600 13,824 75,264 41 114 108 504 24 112 ...
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... I/Os available is reduced by one. 7. "G" indicates RoHS-compliant packages. Refer to "G" in the part number. IGLOOe FPGAs Package Sizes Dimensions Package Length × Width (mm × mm) 2 Nominal Area (mm ) Pitch (mm) Height (mm AGLE600 I/O Types Single-Ended Differential 1 I/O I/O Pairs 165 79 270 135 – ...
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... V2 Speed Grade Blank = Standard Supply Voltage 1.5 V only Part Number IGLOOe Devices AGLE600 = 600,000 System Gates AGLE3000 = 3,000,000 System Gates IGLOOe Devices with Cortex-M1 M1AGLE3000 = 3,000,000 System Gates Notes: 1. Marking Information: IGLOO V2 devices do not have V2 marking, but IGLOO V5 devices are marked accordingly. ...
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... I = Industrial temperature range: –40°C to 85°C ambient temperature. References made to IGLOOe devices also apply to ARM-enabled IGLOOe devices. The ARM-enabled part numbers start with M1 (Cortex-M1). Contact your local Actel representative for device availability: http://www.actel.com/contact/default.aspx AGLE600 – 1 – ...
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IGLOOe Device Family Overview General Description The IGLOOe family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA, a single-chip solution, small footprint packages, reprogrammability, and an abundance of advanced features. The Flash*Freeze ...
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IGLOOe Device Family Overview Flash Advantages Low Power Flash-based IGLOOe devices exhibit power characteristics similar to those of an ASIC, making them an ideal choice for power-sensitive applications. IGLOOe devices have only a very limited power-on current surge and no ...
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Reduced Cost of Ownership Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-based FPGAs, Flash-based IGLOOe devices allow all functionality to be live at power-up; no external boot PROM is required. On-board security ...
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IGLOOe Device Family Overview In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming of IGLOOe devices via an IEEE 1532 JTAG interface. ISP AES User Nonvolatile Decryption* FlashRom Figure 1-1 • IGLOOe Device Architecture Overview Flash*Freeze ...
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IGLOOe device. Refer to illustration of entering/exiting Flash*Freeze mode. Flash*Freeze Mode Control Figure 1-2 • IGLOOe Flash*Freeze Mode VersaTiles The IGLOOe core consists of VersaTiles, which have been enhanced beyond the ...
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IGLOOe Device Family Overview The FlashROM can be programmed via the JTAG programming interface, and its contents can be read back either through the JTAG programming interface or via direct FPGA core addressing. Note that the FlashROM can only be ...
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Global Clocking IGLOOe devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network. Each VersaTile input and output port has access to nine VersaNets: ...
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IGLOOe Device Family Overview Part Number and Revision Date Part Number 51700096-001-2 Revised July 2008 List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version v1 result ...
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IGLOOe DC and Switching Characteristics General Specifications DC and switching characteristics for –F speed grade targets are based only on simulation. The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some ...
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IGLOOe DC and Switching Characteristics Table 2-2 • Recommended Operating Conditions Symbol T Ambient Temperature A T Junction Temperature core supply CC 1 voltage 1.2 V–1.5 V wide range core 2 voltage V JTAG DC ...
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Table 2-4 • Overshoot and Undershoot Limits Average V –GND Overshoot or Undershoot Duration CCI Percentage of Clock Cycle CCI 2 less 3 V 3.3 V 3.6 V Notes: 1. Based on reliability requirements at ...
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IGLOOe DC and Switching Characteristics PLL Behavior at Brownout Condition Actel recommends using monotonic power supplies or voltage regulators to ensure proper powerup behavior. Power ramp-up should be monotonic at least until V brownout activation levels. The V and Figure ...
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CCI where VT can be from 0. 0.9 V (typically 0. 1.575 V CC Region 1: I/O Buffers are OFF Activation trip ...
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IGLOOe DC and Switching Characteristics Package Thermal Characteristics The device junction-to-case thermal resistivity is θ resistivity is θ . The thermal characteristics for θ ja maximum junction temperature is 100°C. maximum power dissipation allowed for an 896-pin FBGA package at ...
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... Values do not include I/O static contribution (P CCPLL ), IGLOOe Sleep Mode ( V AGLE600 1.2 V 1.7 1.8 1.9 2.2 2.5 currents. Values do not include I/O static contribution (P ), IGLOOe Shutdown Mode ( AGLE600 AGLE3000 0 , and V currents. Values do not include I/O static contribution (P CCPLL Units 95 µA 310 µA DC6 AGLE3000 Units 1.7 µA 1.8 µ ...
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... Notes calculate total device I , multiply the number of banks used Includes and V CC CCPLL PUMP 3. Per bank CCI JTAG 4. Values do not include I/O static contribution ( Core Voltage AGLE600 1 1 1.2 V 1.7 1 1.5 V 1.8 1 1.5 V 1.9 1 1.5 V 2.2 1 1.5 V 2.5 CCI currents. and P ) ...
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Power per I/O Pin Table 2-12 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings Single-Ended 3.3 V LVTTL/LVCMOS 3.3 V LVTTL/LVCMOS – Schmitt trigger 2.5 V LVCMOS 2.5 V LVCMOS – Schmitt trigger 1.8 ...
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IGLOOe DC and Switching Characteristics Table 2-13 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings Single-Ended 3.3 V LVTTL/LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) 4 1.2 V LVCMOS 3.3 ...
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... Device-Specific Dynamic Contributions (µW/MHz) AGLE600 AGLE3000 19.7 12.77 4.16 1.85 0.88 0.11 0.057 0.207 0.207 0.7 See Table 2-12 on page 2-9. See Table 2-13 on page 2-10. 25.00 30.00 2.70 AGLE600 AGLE3000 See Table 2-11 on page 2-8. See Table 2-10 on page 2-7. See Table 2-8 on page 2-7. 1.84 See Table 2-11 on page 2-8. See Table 2-12 on page 2-9. See Table 2-13 on page 2-10 ...
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... Device-Specific Dynamic Contributions (µW/MHz) AGLE600 AGLE3000 12.61 8.17 2.66 1.18 0.56 0.071 0.045 0.186 0.109 0.449 See Table 2-8 on page 2-7. See Table 2-9 on page 2-7 and Table 2-10 on page 2-7. 25.00 30.00 2.10 AGLE600 AGLE3000 See Table 2-11 on page 2-8. See Table 2-10 on page 2-7. See Table 2-8 on page 2-7. 0.90 See Table 2-11 on page 2-8. See Table 2-12 on page 2-9. See Table 2-13 on page 2-10. ...
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Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in the Libero IDE software. The power calculation methodology described below uses the ...
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IGLOOe DC and Switching Characteristics Combinatorial Cells Contribution— C-CELL C-CELL N is the number of VersaTiles used as combinatorial modules in the design. C-CELL α is the toggle rate of VersaTile outputs—guidelines are provided in 1 ...
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Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock percentage. If the toggle rate of a net is 100%, this means that this net switches at ...
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IGLOOe DC and Switching Characteristics User I/O Characteristics Timing Model I/O Module (Registered 1. LVPECL 0.43 ns ICLKQ t = 0.47 ns ISUD Input LVTTL/LVCMOS 3.3 V Clock t = 1.10 ns ...
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PY PAD t = MAX DIN V trip PAD 50 GND PY (R) t PYS (R) DIN GND Figure 2-4 • Input Buffer Timing Model and Delays (example CLK I/O Interface ...
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IGLOOe DC and Switching Characteristics D CLK D From Array I/O Interface D DOUT PAD Figure 2-5 • Output Buffer Model and Delays (example DOUT Q DOUT t = MAX MAX(t DOUT ...
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EOUT D Q CLK CLK D I/O Interface D 50 EOUT (R) 50% EOUT t ZL PAD V trip 50 EOUT ( 50% EOUT t ZLS PAD ...
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IGLOOe DC and Switching Characteristics Overview of I/O Performance Summary of I/O DC Input and Output Levels – Default I/O Software Settings Table 2-20 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial ...
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Table 2-21 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions DC I/O Standards 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3 1.2 V LVCMOS ...
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IGLOOe DC and Switching Characteristics Summary of I/O Timing Characteristics – Default I/O Software Settings Table 2-22 • Summary of AC Measuring Points Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS ...
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Table 2-24 • Summary of I/O Timing Characteristics—Software Default Settings Std. Speed Grade, Commercial-Case Conditions: T Worst-Case V = 3.0 V CCI I/O Standard 3.3 V LVTTL / 12 mA High 5 3.3 V LVCMOS 2.5 V LVCMOS 12 mA ...
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IGLOOe DC and Switching Characteristics Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings Std. Speed Grade, Commercial-Case Conditions: T Worst-Case V = 3.0 V CCI I/O Standard 3.3 V LVTTL / 12 mA High 3.3 V LVCMOS 2.5 ...
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Detailed I/O DC Characteristics Table 2-26 • Input Capacitance Symbol Definition C Input capacitance IN C Input capacitance on the clock pin INCLK Table 2-27 • I/O Output Buffer Maximum Resistances Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 ...
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IGLOOe DC and Switching Characteristics Table 2-27 • I/O Output Buffer Maximum Resistances Standard 2.5 V GTL+ HSTL (I) HSTL (II) SSTL2 (I) SSTL2 (II) SSTL3 (I) SSTL3 (II) Notes: 1. These maximum values are provided for informational reasons only. ...
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Table 2-29 • I/O Short Currents I /I OSH Drive Strength 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 3.3 V PCI/PCIX Per PCI/PCI-X Specification 3.3 V GTL 2.5 ...
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IGLOOe DC and Switching Characteristics The length of time an I/O can withstand I reliability data below is based I/O setting, which is the worst case for this type of analysis. For example, at ...
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Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor–Transistor Logic is a general purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. The 3.3 V LVCMOS standard is supported ...
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IGLOOe DC and Switching Characteristics Timing Characteristics 1 Core Voltage Table 2-35 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Drive Strength Speed Grade t ...
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V DC Core Voltage Table 2-37 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Drive Strength Speed Grade t DOUT 4 mA Std. 1.55 5.53 0.26 ...
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IGLOOe DC and Switching Characteristics 2.5 V LVCMOS Low-Voltage CMOS for 2 extension of the LVCMOS standard (JESD8-5) used for general- purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer. Table ...
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Timing Characteristics 1 Core Voltage Table 2-41 • 2.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Drive Strength Speed Grade t DOUT 4 mA Std. 0. Std. 0.98 ...
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IGLOOe DC and Switching Characteristics 1 Core Voltage Table 2-43 • 2.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Speed Drive Strength Grade t DOUT 4 mA Std. 1.55 8 ...
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V LVCMOS Low-Voltage CMOS for 1 extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. Table 2-45 • Minimum and ...
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IGLOOe DC and Switching Characteristics Timing Characteristics 1 Core Voltage Table 2-47 • 1.8 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Speed Drive Strength Grade t DOUT 2 mA Std. ...
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V DC Core Voltage Table 2-49 • 1.8 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Speed Drive Strength Grade t t DOUT Std. 1.55 8. Std. ...
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IGLOOe DC and Switching Characteristics 1.5 V LVCMOS (JESD8-11) Low-Voltage CMOS for 1 extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output ...
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Timing Characteristics 1 Core Voltage Table 2-53 • 1.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Speed Drive Strength Grade t t DOUT Std. 0.98 7.82 4 ...
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IGLOOe DC and Switching Characteristics 1 Core Voltage Table 2-55 • 1.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Speed Drive Strength Grade t DOUT 2 mA Std. 1.55 4 ...
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V LVCMOS (JESD8-12A) Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V applications. It uses a 1.2 V input buffer and a push-pull output buffer. Table 2-57 • Minimum and Maximum DC ...
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IGLOOe DC and Switching Characteristics 3.3 V PCI, 3.3 V PCI-X Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus applications. Table 2-61 • Minimum and Maximum DC Input and Output Levels ...
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Timing Characteristics 1 Core Voltage Table 2-63 • 3.3 V PCI/PCI-X – Applies to 1 Core Voltage Commercial-Case Conditions: T Speed Grade DOUT DP DIN Std. 0.98 2.44 0.19 Note: For specific junction ...
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IGLOOe DC and Switching Characteristics Voltage-Referenced I/O Characteristics 3.3 V GTL Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The V 3.3 V. Table 2-65 • Minimum ...
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Timing Characteristics 1 Core Voltage Table 2-67 • 3.3 V GTL – Applies to 1 Core Voltage Commercial-Case Conditions: T Worst-Case CCI Speed Grade t t DOUT DP Std. 0.98 1.83 ...
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IGLOOe DC and Switching Characteristics 2.5 V GTL Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The V 2.5 V. Table 2-69 • Minimum and Maximum DC ...
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Timing Characteristics 1 Core Voltage Table 2-71 • 2.5 V GTL – Applies to 1 Core Voltage Commercial-Case Conditions: T Worst-Case CCI Speed Grade t t DOUT DP Std. 0.98 1.90 ...
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IGLOOe DC and Switching Characteristics 3.3 V GTL+ Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The V 3.3 V Table 2-73 • Minimum and Maximum ...
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Timing Characteristics 1 Core Voltage Table 2-75 • 3.3 V GTL+ – Applies to 1 Core Voltage Commercial-Case Conditions: T Worst-Case CCI Speed Grade t t DOUT DP Std. 0.98 1.85 ...
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IGLOOe DC and Switching Characteristics 2.5 V GTL+ Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The V 2.5 V. Table 2-77 • Minimum and Maximum ...
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Timing Characteristics 1 Core Voltage Table 2-79 • 2.5 V GTL+ – Applies to 1 Core Voltage Commercial-Case Conditions: T Worst-Case CCI Speed Grade t t DOUT DP Std. 0.98 1.97 ...
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IGLOOe DC and Switching Characteristics HSTL Class I High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). IGLOOe devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-81 • ...
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Timing Characteristics 1 Core Voltage Table 2-83 • HSTL Class I – Applies to 1 Core Voltage Commercial-Case Conditions: T Worst-Case CCI Speed Grade t t DOUT DP Std. 0.98 2.74 ...
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IGLOOe DC and Switching Characteristics HSTL Class II High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). IGLOOe devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-85 • ...
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Timing Characteristics 1 Core Voltage Table 2-87 • HSTL Class II – Applies to 1 Core Voltage Commercial-Case Conditions: T Worst-Case CCI Speed Grade t t DOUT DP Std. 0.98 2.62 ...
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IGLOOe DC and Switching Characteristics SSTL2 Class I Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). IGLOOe devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-89 • Minimum and ...
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Timing Characteristics 1 Core Voltage Table 2-91 • SSTL 2 Class I – Applies to 1 Core Voltage Commercial-Case Conditions: T Worst-Case CCI Speed Grade t t DOUT DP Std. 0.98 ...
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IGLOOe DC and Switching Characteristics SSTL2 Class II Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). IGLOOe devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-93 • Minimum and ...
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SSTL3 Class I Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). IGLOOe devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-97 • Minimum and Maximum DC Input and Output ...
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IGLOOe DC and Switching Characteristics Timing Characteristics 1 Core Voltage Table 2-99 • SSTL 3 Class I – Applies to 1 Core Voltage Commercial-Case Conditions: T Worst-Case CCI Speed Grade t ...
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SSTL3 Class II Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). IGLOOe devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-101 • Minimum and Maximum DC Input and Output ...
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IGLOOe DC and Switching Characteristics Timing Characteristics 1 Core Voltage Table 2-103 • SSTL 3 Class II – Applies to 1 Core Voltage Commercial-Case Conditions: T Worst-Case CCI Speed Grade t ...
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Differential I/O Characteristics Physical Implementation Configuration of the I/O modules as a differential pair is handled by the Actel Designer software when the user instantiates a differential I/O macro in the design. Differential I/Os can also be used in conjunction ...
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IGLOOe DC and Switching Characteristics Table 2-105 • Minimum and Maximum DC Input and Output Levels DC Parameter V Supply Voltage CCI V Output LOW Voltage OL V Output HIGH Voltage Output Lower Current ...
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BLVDS/M-LVDS Bus LVDS (BLVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers. Actel LVDS drivers provide the higher drive ...
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IGLOOe DC and Switching Characteristics Table 2-109 • Minimum and Maximum DC Input and Output Levels DC Parameter Description V Supply Voltage CCI V Output LOW Voltage OL V Output HIGH Voltage Input LOW, Input HIGH ...
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I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset Preset Data D C DFN1E1P1 E Enable B CLK A Data Input I/O Register with: Active High Enable Active High Preset Positive-Edge Triggered Figure 2-26 • Timing ...
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IGLOOe DC and Switching Characteristics Table 2-113 • Parameter Definition and Measuring Nodes Parameter Name t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD t Data Hold Time for the Output ...
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Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear D Data CC DFN1E1C1 E Enable BB CLK AA CLR DD Data Input I/O Register with Active High Enable Active High Clear Positive-Edge Triggered Figure 2-27 • Timing Model of ...
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IGLOOe DC and Switching Characteristics Table 2-114 • Parameter Definition and Measuring Nodes Parameter Name t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD t Data Hold Time for the Output ...
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Input Register 50% 50% CLK t ISUD 50% 1 Data Enable 50% t IHE t Preset ISUE Clear Out_1 Figure 2-28 • Input Register Timing Diagram Timing Characteristics 1 Core Voltage Table 2-115 • Input Data Register Propagation ...
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IGLOOe DC and Switching Characteristics 1 Core Voltage Table 2-116 • Input Data Register Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of the Input Data Register ICLKQ t Data Setup Time for the Input Data Register ISUD ...
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Output Register 50% 50% CLK 50% 1 Data_out Enable 50% t OHE t Preset OSUE Clear DOUT Figure 2-29 • Output Register Timing Diagram Timing Characteristics 1 Core Voltage Table 2-117 • Output Data Register Propagation Delays Commercial-Case ...
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IGLOOe DC and Switching Characteristics 1 Core Voltage Table 2-118 • Output Data Register Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD ...
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Output Enable Register 50% 50% CLK t OESUD 1 50% D_Enable 50% Enable t t OESUE OEHE Preset Clear EOUT t Figure 2-30 • Output Enable Register Timing Diagram Timing Characteristics 1 Core Voltage Table 2-119 • Output ...
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IGLOOe DC and Switching Characteristics 1 Core Voltage Table 2-120 • Output Enable Register Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of the Output Enable Register OECLKQ t Data Setup Time for the Output Enable Register OESUD ...
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DDR Module Specifications Input DDR Module INBUF A Data B CLK CLKBUF C CLR INBUF Figure 2-31 • Input DDR Timing Model Table 2-121 • Parameter Definitions Parameter Name t Clock-to-Out Out_QR DDRICLKQ1 t Clock-to-Out Out_QF DDRICLKQ2 t Data Setup ...
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IGLOOe DC and Switching Characteristics CLK Data 1 2 CLR t DDRIREMCLR t DDRICLR2Q1 Out_QF t DDRICLR2Q2 Out_QR Figure 2-32 • Input DDR Timing Diagram Timing Characteristics 1 Core Voltage Table 2-122 • Input DDR Propagation Delays Commercial-Case ...
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V DC Core Voltage Table 2-123 • Input DDR Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Out Out_QR for Input DDR DDRICLKQ1 t Clock-to-Out Out_QF for Input DDR DDRICLKQ2 t Data Setup for Input DDR (negedge) DDRISUD1 t Data ...
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IGLOOe DC and Switching Characteristics Output DDR Module Data_F (from core) CLK CLKBUF Data_R (from core) CLR INBUF Figure 2-33 • Output DDR Timing Model Table 2-124 • Parameter Definitions Parameter Name t Clock-to-Out DDROCLKQ t Asynchronous Clear-to-Out DDROCLR2Q t ...
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CLK Data_F DDROREMCLR Data_R CLR DDROREMCLR t DDROCLR2Q Out Figure 2-34 • Output DDR Timing Diagram IGLOOe DC and Switching Characteristics t t DDROHD2 DDROSUD2 DDROHD1 DDROCLKQ 7 ...
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IGLOOe DC and Switching Characteristics Timing Characteristics 1 Core Voltage Table 2-125 • Output DDR Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Out of DDR for Output DDR DDROCLKQ t Data_F Data Setup for Output DDR DDROSUD1 t ...
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VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The IGLOOe library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the Fusion, and ProASIC3 ...
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IGLOOe DC and Switching Characteristics Fanout = 4 Length = 1 VersaTile Length = 1 VersaTile Length = 1 VersaTile Length = 1 VersaTile 50 OUT GND V CC OUT Figure 2-36 • Timing Model and Waveforms ...
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Timing Characteristics 1 Core Voltage Table 2-127 • Combinatorial Cell Propagation Delays Commercial-Case Conditions: T Combinatorial Cell INV AND2 NAND2 OR2 NOR2 XOR2 MAJ3 XOR3 MUX2 AND3 Note: For specific junction temperature and voltage supply levels, refer to ...
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IGLOOe DC and Switching Characteristics VersaTile Specifications as a Sequential Module The IGLOOe library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input and optional enable, clear, or preset. In this section, timing ...
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CLK t SUD 50% Data EN 50 PRE SUE CLR Out t CLKQ Figure 2-38 • Timing Model and Waveforms Timing Characteristics 1 Core Voltage Table 2-129 • Register Delays Commercial-Case Conditions: T ...
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IGLOOe DC and Switching Characteristics 1 Core Voltage Table 2-130 • Register Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of the Core Register CLKQ t Data Setup Time for the Core Register SUD t Data Hold Time for ...
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... Clock delays are device-specific. The global tree presented in device used to drive all D-flip-flops in the device. CCC Figure 2-39 • Example of Global Tree Use in an AGLE600 Device for Clock Routing IGLOOe DC and Switching Characteristics Figure 2- example of a global tree used for clock routing. ...
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... Minimum and maximum delays are measured with minimum and maximum loading. Timing Characteristics 1 Core Voltage Table 2-131 • AGLE600 Global Resource Commercial-Case Conditions: T Parameter t Input LOW Delay for Global Clock ...
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... V DC Core Voltage Table 2-133 • AGLE600 Global Resource Commercial-Case Conditions: T Parameter t Input LOW Delay for Global Clock RCKL t Input HIGH Delay for Global Clock RCKH t Minimum Pulse Width HIGH for Global Clock RCKMPWH t Minimum Pulse Width LOW for Global Clock ...
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IGLOOe DC and Switching Characteristics Clock Conditioning Circuits CCC Electrical Specifications Timing Characteristics Table 2-135 • IGLOOe CCC/PLL Specification For IGLOOe Devices, 1 Core Supply Voltage Parameter Clock Conditioning Circuitry Input Frequency f Clock Conditioning ...
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Table 2-136 • IGLOOe CCC/PLL Specification For IGLOOe V2 Devices, 1 Core Supply Voltage Parameter Clock Conditioning Circuitry Input Frequency f Clock Conditioning Circuitry Output Frequency f 4 Serial Clock (SCLK) for Dynamic PLL Delay Increments in Programmable ...
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IGLOOe DC and Switching Characteristics Embedded SRAM and FIFO Characteristics SRAM Figure 2-41 • RAM Models RAM4K9 RADDR8 ADDRA11 DOUTA8 RADDR7 DOUTA7 ADDRA10 ADDRA0 DOUTA0 RADDR0 DINA8 DINA7 RW1 DINA0 RW0 WIDTHA1 WIDTHA0 PIPE PIPEA WMODEA BLKA ...
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Timing Waveforms t CKH CLK ADD 0 t BKS BLK_B t ENS WEN_B Figure 2-42 • RAM Read for Pass-Through Output t CKH CLK ADD 0 t ...
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IGLOOe DC and Switching Characteristics t CKH CLK ADD 0 t BKS BLK_B t ENS WEN_B Figure 2-44 • RAM Write, Output Retained (WMODE = 0) CLK ADD ...
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CLK1 ADD1 DI1 1 t CCKH CLK2 WEN_B1 WEN_B2 ADD2 DI2 D DO2 D (pass-through) DO2 D (pipelined) Figure 2-46 • Write Access after Write onto Same Address A ...
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IGLOOe DC and Switching Characteristics CLK1 ADD1 DI1 CLK2 WEN_B1 WEN_B2 ADD2 DO2 (pass-through) DO2 (pipelined) Figure 2-47 • Read Access after Write onto Same Address ...
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CLK1 ADD1 0 WEN_B1 t CKQ1 DO1 D n (pass-through) DO1 D (pipelined CCKH CLK2 ADD2 A D DI2 WEN_B2 Figure 2-48 • Write Access after Read onto Same Address t CKH CLK ...
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IGLOOe DC and Switching Characteristics Timing Characteristics Applies to 1 Core Voltage Table 2-137 • RAM4K9 Commercial-Case Conditions: T Parameter t Address Setup Time AS t Address Hold Time AH t REN_B, WEN_B Setup Time ENS t REN_B, ...
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Table 2-138 • RAM512X18 Commercial-Case Conditions: T Parameter t Address Setup Time AS t Address Hold Time AH t REN_B, WEN_B Setup Time ENS t REB_B, WEN_B Hold Time ENH t Input Data (DI) Setup Time DS t Input Data ...
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IGLOOe DC and Switching Characteristics Applies to 1 Core Voltage Table 2-139 • RAM4K9 Commercial-Case Conditions: T Parameter t Address Setup Time AS t Address Hold Time AH t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold ...
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Table 2-140 • RAM512X18 Commercial-Case Conditions: T Parameter t Address Setup Time AS t Address Hold Time AH t REN_B, WEN_B Setup Time ENS t REB_B, WEN_B Hold Time ENH t Input Data (DI) Setup Time DS t Input Data ...
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IGLOOe DC and Switching Characteristics FIFO Figure 2-50 • FIFO Model FIFO4K18 RW2 RD17 RW1 RD16 RW0 WW2 WW1 RD0 WW0 ESTOP FULL FSTOP AFULL EMPTY AEVAL11 AEMPTY AEVAL10 AEVAL0 AFVAL11 AFVAL10 AFVAL0 REN RBLK RCLK ...
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Timing Waveforms RCLK/ WCLK RESET_B t RSTFG EMPTY AEMPTY t RSTFG FULL AFULL WA/RA (Address Counter) Figure 2-51 • FIFO Reset RCLK EMPTY AEMPTY WA/RA NO MATCH (Address Counter) Figure 2-52 • FIFO EMPTY Flag and AEMPTY Flag Assertion IGLOOe ...
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IGLOOe DC and Switching Characteristics WCLK FULL AFULL WA/RA NO MATCH (Address Counter) Figure 2-53 • FIFO FULL Flag and AFULL Flag Assertion WCLK WA/RA MATCH NO MATCH (EMPTY) (Address Counter) 1st Rising Edge After 1st Write RCLK EMPTY AEMPTY ...
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Timing Characteristics Applies to 1 Core Voltage Table 2-141 • FIFO Commercial-Case Conditions: T Parameter t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup Time BKS t BLK_B Hold Time BKH t ...
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IGLOOe DC and Switching Characteristics Applies to 1 Core Voltage Table 2-142 • FIFO Commercial-Case Conditions: T Parameter t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup Time BKS t BLK_B Hold ...
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Embedded FlashROM Characteristics t SU CLK t HOLD Address A 0 Data Figure 2-56 • Timing Diagram Timing Characteristics Applies to 1 Core Voltage Table 2-143 • Embedded FlashROM Access Time Commercial-Case Conditions: T Parameter t Address Setup ...
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IGLOOe DC and Switching Characteristics JTAG 1532 Characteristics JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the Characteristics" section ...
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Part Number and Revision Date Part Number 51700096-002-2 Revised July 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version Advance v0 result of the Libero ...
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IGLOOe DC and Switching Characteristics Previous Version Advance v0.1 Table 2-13 · Summary of I/O Output Buffer Power (per pin) – Default I/O (continued) Software Settings1 updated to reflect that power was measured on V Table 2-15 · Different Consumption ...
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Previous Version Advance v0.3 Table 3-99 • Minimum and Maximum DC Input and Output Levels was (continued) updated. Table 3-136 • JTAG 1532 and Table 3-135 • JTAG 1532 were updated. Advance v0.1 The T parameter in Table 3-2 • ...
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Package Pin Assignments 256-Pin FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner ...
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... D14 GBB2/IO37PDB2V0 D15 IO39PDB2V0 D16 IO39NDB2V0 E1 IO128NDB7V1 E2 IO129NDB7V1 E3 IO132NDB7V1 E4 IO130PDB7V1 E5 VMV0 CCI CCI v1.1 256-Pin FBGA Pin Number AGLE600 Function E8 IO13NDB0V2 E9 IO21NDB1V0 E10 V B1 CCI E11 V B1 CCI E12 VMV1 E13 GBC2/IO38PDB2V0 E14 IO37NDB2V0 E15 IO41NDB2V0 E16 IO41PDB2V0 F1 IO124PDB7V0 F2 IO125PDB7V0 ...
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... V CC L11 GND L12 V B3 CCI L13 GDB0/IO66NPB3V1 L14 IO60NDB3V1 L15 IO60PDB3V1 L16 IO61PDB3V1 M1 IO109NPB6V0 M2 IO106NDB6V0 M3 IO106PDB6V0 v1.1 IGLOOe Packaging 256-Pin FBGA Pin Number AGLE600 Function M4 GEC0/IO104NPB6V0 M5 VMV5 CCI CCI M8 IO84NDB5V0 M9 IO84PDB5V0 M10 V B4 CCI M11 V B4 CCI M12 VMV3 ...
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... R12 IO69NDB4V0 R13 GDB2/IO69PDB4V0 R14 TDI R15 GNDQ R16 TDO T1 GND T2 IO100NDB5V2 T3 FF/GEB2/IO100PDB5 V2 T4 IO99NDB5V2 T5 IO88NDB5V0 T6 IO88PDB5V0 T7 IO89NSB5V0 T8 IO80NSB4V1 T9 IO81NDB4V1 3 -4 256-Pin FBGA Pin Number AGLE600 Function T10 IO81PDB4V1 T11 IO70NDB4V0 T12 GDC2/IO70PDB4V0 T13 IO68NDB4V0 T14 GDA2/IO68PDB4V0 T15 TMS T16 GND v1.1 ...
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FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner ...
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... AB19 NC AB20 V B4 CCI AB21 GND AB22 GND B1 GND CCI IO03NDB0V0 B5 IO03PDB0V0 B6 IO07NDB0V1 v1.1 484-Pin FBGA Pin Number AGLE600 Function B7 IO07PDB0V1 B8 IO11NDB0V1 B9 IO17NDB0V2 B10 IO14PDB0V2 B11 IO19PDB0V2 B12 IO22NDB1V0 B13 IO26NDB1V0 B14 NC B15 NC B16 IO30NDB1V1 B17 IO30PDB1V1 B18 IO32PDB1V1 B19 NC ...
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... F15 GBC0/IO33NDB1V1 F16 V CCPLB F17 VMV2 F18 IO36NDB2V0 F19 IO42PDB2V0 F20 NC F21 NC F22 NC G1 IO127NDB7V1 G2 IO127PDB7V1 v1.1 IGLOOe Packaging 484-Pin FBGA Pin Number AGLE600 Function IO128PDB7V1 G5 IO129PDB7V1 G6 GAC2/IO132PDB7V COMPLA G8 GNDQ G9 IO09NDB0V1 G10 IO09PDB0V1 G11 IO13PDB0V2 G12 IO21PDB1V0 G13 IO25PDB1V0 G14 ...
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... L11 GND L12 GND L13 GND L14 V CC L15 GCC0/IO50NPB2V1 L16 GCB1/IO51PPB2V1 L17 GCA0/IO52NPB3V0 L18 V COMPLC L19 GCB0/IO51NPB2V1 L20 IO49PPB2V1 v1.1 484-Pin FBGA Pin Number AGLE600 Function L21 IO47NDB2V1 L22 IO47PDB2V1 IO114NPB6V1 M3 IO117NDB6V1 M4 GFA2/IO117PDB6V1 M5 GFA1/IO118PDB6V1 M6 V CCPLF M7 IO116NDB6V1 M8 GFB2/IO116PDB6V1 M10 ...
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... T10 IO92NDB5V1 T11 IO90NDB5V1 T12 IO82NDB5V0 T13 IO74NDB4V1 T14 IO74PDB4V1 T15 GNDQ T16 V COMPLD T17 V JTAG T18 GDC0/IO65NDB3V1 v1.1 IGLOOe Packaging 484-Pin FBGA Pin Number AGLE600 Function T19 GDA1/IO67PDB3V1 T20 NC T21 IO64PDB3V1 T22 IO62NDB3V1 IO107PDB6V0 U3 IO107NDB6V0 U4 GEB1/IO103PDB6V0 U5 GEB0/IO103NDB6V 0 U6 VMV6 U7 V CCPLE ...
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... W11 IO80NDB4V1 W12 IO81NDB4V1 W13 IO81PDB4V1 W14 IO70NDB4V0 W15 GDC2/IO70PDB4V0 W16 IO68NDB4V0 W17 GDA2/IO68PDB4V0 W18 TMS W19 GND W20 NC W21 484-Pin FBGA Pin Number AGLE600 Function W22 CCI IO98NDB5V2 Y5 GND Y6 IO94NDB5V1 Y7 IO94PDB5V1 ...
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FBGA Pin Number AGLE3000 Function A1 GND A2 GND CCI A4 IO10NDB0V1 A5 IO10PDB0V1 A6 IO16NDB0V1 A7 IO16PDB0V1 A8 IO18PDB0V2 A9 IO24PDB0V2 A10 IO28NDB0V3 A11 IO28PDB0V3 A12 IO46PDB1V0 A13 IO54PDB1V1 A14 IO56NDB1V1 A15 IO56PDB1V1 A16 IO64NDB1V2 ...
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Package Pin Assignments 484-Pin FBGA Pin Number AGLE3000 Function C21 IO94PPB2V1 C22 V B2 CCI D1 IO293PDB7V2 D2 IO303NDB7V3 D3 IO305NDB7V3 D4 GND D5 GAA0/IO00NDB0V0 D6 GAA1/IO00PDB0V0 D7 GAB0/IO01NDB0V0 D8 IO20PDB0V2 D9 IO22PDB0V2 D10 IO30PDB0V3 D11 IO38NDB0V4 D12 IO52NDB1V1 D13 ...
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FBGA Pin Number AGLE3000 Function H19 IO100PDB2V2 H20 V CC H21 VMV2 H22 IO105PDB2V2 J1 IO285NDB7V1 J2 IO285PDB7V1 J3 VMV7 J4 IO279PDB7V0 J5 IO283PDB7V1 J6 IO281PDB7V0 J7 IO287NDB7V1 CCI J9 GND J10 V CC J11 V ...
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Package Pin Assignments 484-Pin FBGA Pin Number AGLE3000 Function N17 IO132NPB3V2 N18 IO117NPB3V0 N19 IO132PPB3V2 N20 GNDQ N21 IO126NDB3V1 N22 IO128PDB3V1 P1 IO247PDB6V1 P2 IO253PDB6V2 P3 IO270NPB6V4 P4 IO261NPB6V3 P5 IO249PPB6V1 P6 IO259PDB6V3 P7 IO259NDB6V3 CCI P9 ...
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FBGA Pin Number AGLE3000 Function V15 IO155NDB4V0 V16 GDB2/IO155PDB4V0 V17 TDI V18 GNDQ V19 TDO V20 GND V21 IO146PDB3V4 V22 IO142NDB3V3 W1 IO239NDB6V0 W2 IO237PDB6V0 W3 IO230PSB5V4 W4 GND W5 IO232NDB5V4 W6 FF/GEB2/IO232PDB5V 4 W7 IO231NDB5V4 W8 IO214NDB5V2 W9 ...
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Package Pin Assignments 896-Pin FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx ...
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FBGA AGLE3000 Pin Number Function A2 GND A3 GND A4 IO14NPB0V1 A5 GND A6 IO07NPB0V0 A7 GND A8 IO09NDB0V1 A9 IO17NDB0V2 A10 IO17PDB0V2 A11 IO21NDB0V2 A12 IO21PDB0V2 A13 IO33NDB0V4 A14 IO33PDB0V4 A15 IO35NDB0V4 A16 IO35PDB0V4 A17 IO41NDB1V0 A18 IO43NDB1V0 ...
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Package Pin Assignments 896-Pin FBGA AGLE3000 Pin Number Function AC18 IO182PPB4V3 AC19 IO170NPB4V2 AC20 IO164NDB4V1 AC21 IO164PDB4V1 AC22 IO162PPB4V1 AC23 GND AC24 V COMPLD AC25 IO150NDB3V4 AC26 IO148NDB3V4 AC27 GDA1/IO153PDB3V4 AC28 IO145NDB3V3 AC29 IO143NDB3V3 AC30 IO137NDB3V2 AD1 GND AD2 IO242NPB6V1 ...
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FBGA AGLE3000 Pin Number Function AF29 GNDQ AF30 GND AG1 IO238NPB6V0 AG2 V CC AG3 IO232NPB5V4 AG4 GND AG5 IO220PPB5V3 AG6 IO228PDB5V4 AG7 IO231NDB5V4 AG8 GEC2/IO231PDB5V4 AG9 IO225NPB5V3 AG10 IO223NPB5V3 AG11 IO221PDB5V3 AG12 IO221NDB5V3 AG13 IO205NPB5V1 AG14 IO199NDB5V0 AG15 ...
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Package Pin Assignments 896-Pin FBGA AGLE3000 Pin Number Function AK14 IO197PDB5V0 AK15 IO191NDB4V4 AK16 IO191PDB4V4 AK17 IO189NDB4V4 AK18 IO189PDB4V4 AK19 IO179PPB4V3 AK20 IO175NDB4V2 AK21 IO175PDB4V2 AK22 IO169NDB4V1 AK23 IO169PDB4V1 AK24 GND AK25 IO167PPB4V1 AK26 GND AK27 GDC2/IO156PPB4V0 AK28 GND AK29 ...
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FBGA AGLE3000 Pin Number Function D30 GBA2/IO82PPB2V0 E1 GND E2 IO303NPB7V3 CCI E4 IO305PPB7V3 GAC0/IO02NDB0V0 CCI E8 IO06PPB0V0 E9 IO24NDB0V2 E10 IO24PDB0V2 E11 IO13NDB0V1 E12 IO13PDB0V1 E13 IO34NDB0V4 E14 ...
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Package Pin Assignments 896-Pin FBGA AGLE3000 Pin Number Function H11 IO18PDB0V2 H12 IO26NPB0V3 H13 IO28NDB0V3 H14 IO28PDB0V3 H15 IO38PPB0V4 H16 IO42NDB1V0 H17 IO52NDB1V1 H18 IO52PDB1V1 H19 IO62NDB1V2 H20 IO62PDB1V2 H21 IO70NDB1V3 H22 IO70PDB1V3 H23 GND H24 V COMPLB H25 GBC2/IO84PDB2V0 ...
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FBGA AGLE3000 Pin Number Function L26 IO87NDB2V0 L27 IO97PDB2V1 L28 IO101PDB2V2 L29 IO103PDB2V2 L30 IO119NDB3V0 M1 IO282NDB7V1 M2 IO282PDB7V1 M3 IO292NDB7V2 M4 IO292PDB7V2 M5 IO283NDB7V1 M6 IO285PDB7V1 M7 IO287PDB7V1 M8 IO289PDB7V1 M9 IO289NDB7V1 M10 V B7 CCI M11 V ...
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Package Pin Assignments 896-Pin FBGA AGLE3000 Pin Number Function R11 V CC R12 GND R13 GND R14 GND R15 GND R16 GND R17 GND R18 GND R19 GND R20 V CC R21 V B2 CCI R22 GCC0/IO112NDB2V3 R23 GCB2/IO116PDB3V0 R24 ...
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FBGA AGLE3000 Pin Number Function V26 IO126NDB3V1 V27 IO129NDB3V1 V28 IO127NDB3V1 V29 IO125NDB3V1 V30 IO123PDB3V1 W1 IO266NDB6V4 W2 IO262NDB6V3 W3 IO260NDB6V3 W4 IO252NDB6V2 W5 IO251NDB6V2 W6 IO251PDB6V2 W7 IO255NDB6V2 W8 IO249PPB6V1 W9 IO253PDB6V2 W10 V B6 CCI W11 V ...
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Package Pin Assignments Part Number and Revision Date Part Number 51700096-003-1 Revised June 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version v1.0 The naming conventions changed ...
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... Datasheet Categories Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as “Product Brief,” “Advance,” and “Production”. The definition of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information ...
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... Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel Corporation Actel Europe Ltd. 2061 Stierlin Court River Court,Meadows Business Park Mountain View, CA Station Approach, Blackwater 94043-4655 USA Camberley Surrey GU17 9AB United Kingdom Phone 650 ...