AGLE600V2-FGG484 Actel, AGLE600V2-FGG484 Datasheet - Page 38
![no-image](/images/manufacturer_photos/0/0/8/actel_sml.jpg)
AGLE600V2-FGG484
Manufacturer Part Number
AGLE600V2-FGG484
Description
FPGA - Field Programmable Gate Array 600K System Gates
Manufacturer
Actel
Datasheet
1.AGLE600V2-FGG484.pdf
(158 pages)
Specifications of AGLE600V2-FGG484
Processor Series
AGLE600
Core
IP Core
Maximum Operating Frequency
526.32 MHz, 892.86 MHz
Number Of Programmable I/os
270
Data Ram Size
110592
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
600 K
Package / Case
FPBGA-484
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AGLE600V2-FGG484
Manufacturer:
Actel
Quantity:
135
Company:
Part Number:
AGLE600V2-FGG484I
Manufacturer:
Microsemi SoC
Quantity:
10 000
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IGLOOe DC and Switching Characteristics
Table 2-23 • I/O AC Parameter Definitions
2- 24
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
DP
PY
DOUT
EOUT
DIN
PYS
HZ
ZH
LZ
ZL
ZHS
ZLS
Data to Pad delay through the Output Buffer
Pad to Data delay through the Input Buffer with Schmitt trigger disabled
Data to Output Buffer delay through the I/O interface
Enable to Output Buffer Tristate Control delay through the I/O interface
Input Buffer to Data delay through the I/O interface
Pad to Data delay through the Input Buffer with Schmitt trigger enabled
Enable to Pad delay through the Output Buffer—HIGH to Z
Enable to Pad delay through the Output Buffer—Z to HIGH
Enable to Pad delay through the Output Buffer—LOW to Z
Enable to Pad delay through the Output Buffer—Z to LOW
Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH
Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW
R e visio n 8
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