APA300-FGG256 Actel, APA300-FGG256 Datasheet - Page 165

• Manufacturer Part Number: APA300-FGG256
• Description: FPGA - Field Programmable Gate Array 300K System Gates
• Manufacturer: Actel

Specifications of APA300-FGG256

• Processor Series: APA300
• Core: IP Core
• Maximum Operating Frequency: 150 MHz
• Number Of Programmable I/os: 290
• Data Ram Size: 73728
• Supply Voltage (max): 2.7 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: APA-Eval-Kit, APA-Eval-BRD1, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.3 V
• Number Of Gates: 300 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Number
Pin
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
K1
K2
K3
K4
K5
K6
K7
K8
K9
624-Pin CCGA/LGA
Function
APA600
GND
GND
GND
GND
GND
GND
V
GND
V
GND
GND
V
V
V
V
V
V
V
V
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DDP
DDP
DDP
DD
DD
DD
DD
DD
DD
DD
APA1000
Function
GND
GND
GND
GND
GND
GND
V
GND
V
V
GND
GND
V
V
V
V
V
V
V
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DDP
DDP
DDP
DD
DD
DD
DD
DD
DD
DD
Number
K22
K23
K24
K25
Pin
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
M1
M2
M3
M4
M5
M6
L1
L2
L3
L4
L5
L6
L7
L8
L9
624-Pin CCGA/LGA
Function
APA600
I/O / GL2
NPECL1
AGND
V
V
GND
GND
GND
GND
GND
GND
GND
V
V
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DDP
DDP
v5.9
DD
DD
APA1000
Function
I/O / GL2
NPECL1
AGND
V
GND
GND
GND
GND
GND
GND
GND
V
V
V
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DDP
DDP
DD
DD
Number
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
M24
M25
N10
N11
N12
N13
N14
N15
Pin
M7
M8
M9
N1
N2
N3
N4
N5
N6
N7
N8
N9
ProASIC
624-Pin CCGA/LGA
I/O / GLMX1
I/O / GLMX2
Function
PLUS
APA600
I/O / GL4
I/O / GL1
PPECL1 /
NPECL2
AGND
AVDD
Input
V
V
V
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
V
V
V
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DDP
DDP
DDP
DD
DD
DD
Flash Family FPGAs
I/O / GLMX1
I/O / GLMX2
APA1000
Function
I/O / GL4
I/O / GL1
PPECL1 /
NPECL2
AGND
AVDD
Input
V
GND
GND
GND
GND
GND
GND
GND
V
V
GND
GND
GND
GND
GND
GND
V
V
V
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DDP
DDP
DDP
DD
DD
DD
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