APA300-FGG256 Actel, APA300-FGG256 Datasheet - Page 32

• Manufacturer Part Number: APA300-FGG256
• Description: FPGA - Field Programmable Gate Array 300K System Gates
• Manufacturer: Actel

Specifications of APA300-FGG256

• Processor Series: APA300
• Core: IP Core
• Maximum Operating Frequency: 150 MHz
• Number Of Programmable I/os: 290
• Data Ram Size: 73728
• Supply Voltage (max): 2.7 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: APA-Eval-Kit, APA-Eval-BRD1, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.3 V
• Number Of Gates: 300 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note: Each RAM block contains a multiplexer (called DMUX) for each output signal, increasing design efficiency. These DMUX cells do not
Figure 2-18 • Example SRAM Block Diagrams
Table 2-14 • Memory Block SRAM Interface Signals
2 -2 2
SRAM Signal
WCLKS
RCLKS
RADDR<0:7>
RBLKB
RDB
WADDR<0:7>
WBLKB
DI<0:8>
WRB
DO<0:8>
RPE
WPE
PARODD
Note: Not all signals shown are used in all modes.
ProASIC
WADDR <0:7>
WADDR <0:7>
consume any core logic tiles and connect directly to high-speed routing resources between the RAM blocks. They are used when
RAM blocks are cascaded and are automatically inserted by the software tools.
PLUS
DI <0:8>
DI <0:8>
WBLKB
WBLKB
WCLKS
WCLKS
Flash Family FPGAs
WRB
WRB
WPE
WPE
Bits
1
1
8
1
1
8
1
9
1
9
1
1
1
Async Read
Sync Write
Sync Write
Sync Read
PARODD
(256x9)
(256x9)
PARODD
SRAM
SRAM
Ports
Ports
and
and
In/Out
Out
Out
Out
In
In
In
In
In
In
In
In
In
In
DO <0:8>
RADDR <0:7>
RDB
RBLKB
RCLKS
RPE
DO <0:8>
RADDR <0:7>
RDB
RBLKB
RPE
Write clock used on synchronization on write side
Read clock used on synchronization on read side
Read address
Read block select (active Low)
Read pulse (active Low)
Write address
Write block select (active Low)
Input data bits <0:8>, <8> can be used for parity In
Write pulse (active Low)
Output data bits <0:8>, <8> can be used for parity out
Read parity error (active High)
Write parity error (active High)
Selects odd parity generation/detect when High, even parity when Low
v5.9
WADDR <0:7>
WADDR <0:7>
DI <0:8>
DI <0:8>
WBLKB
WBLKB
WRB
WRB
WPE
WPE
Description
Async Write
Async Write
Async Read
Sync Read
(256x9)
PARODD
(256x9)
SRAM
PARODD
SRAM
Ports
Ports
and
and
DO <0:8>
RADDR <0:7>
RDB
RBLKB
RCLKS
RPE
DO <0:8>
RADDR <0:7>
RDB
RBLKB
RCLKS
RPE