A42MX24-PLG84 Actel, A42MX24-PLG84 Datasheet - Page 77

• Manufacturer Part Number: A42MX24-PLG84
• Description: FPGA - Field Programmable Gate Array 36K System Gates
• Manufacturer: Actel

Specifications of A42MX24-PLG84

• Processor Series: A42MX24
• Core: IP Core
• Number Of Macrocells: 912
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 140
• Delay Time: 5.6 ns
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 3 V
• Number Of Gates: 36 K
• Package / Case: PLCC-84
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 38 •
Parameter Description
Input Module Predicted Routing Delays
t
t
t
t
t
Global Clock Network
t
t
t
t
t
t
t
t
f
TTL Output Module Timing
t
t
t
t
t
Notes:
1. For dual-module macros, use t
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
5. Delays based on 35 pF loading.
IRD1
IRD2
IRD3
IRD4
IRD8
CKH
CKL
PWH
PWL
CKSW
SUEXT
HEXT
P
MAX
DLH
DHL
ENZH
ENZL
ENHZ
device performance. Post-route timing analysis or simulation is required to determine actual performance.
obtained from the Timer utility.
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
A42MX36 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, V
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Input LOW to HIGH
Input HIGH to LOW
Minimum Pulse
Width HIGH
Minimum Pulse
Width LOW
Maximum Skew
Input Latch External
Set-Up
Input Latch External
Hold
Minimum Period
(1/f
Maximum Datapath
Frequency
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
MAX
)
5
PD1
FO=32
FO=635
FO=32
FO=635
FO=32
FO=635
FO=32
FO=635
FO=32
FO=635
FO=32
FO=635
FO=32
FO=635
FO=32
FO=635
FO=32
FO=635
+ t
RD1
+ t
2
PDn
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
‘–3’ Speed
1.8
2.0
1.8
2.0
0.0
0.0
2.8
3.3
5.5
6.0
, t
CO
CCA
+ t
180
166
2.0
2.3
2.6
3.0
4.3
2.7
3.0
3.8
4.9
0.8
0.8
2.6
3.0
2.7
3.0
5.3
RD1
= 4.75V, T
+ t
v6.1
‘–2’ Speed
PDn
2.0
2.2
2.0
2.2
0.0
0.0
3.2
3.7
6.1
6.6
, or t
J
= 70°C)
164
151
3.3
PD1
2.2
2.6
2.9
3.3
4.8
3.0
3.3
4.2
5.4
0.8
0.8
2.8
3.3
3.0
5.8
+ t
RD1
‘–1’ Speed
2.2
2.5
2.2
2.5
0.0
0.0
3.6
4.2
6.6
7.2
+ t
SUD
151
139
2.5
2.9
3.3
3.8
5.5
3.4
3.8
4.8
6.1
0.9
0.9
3.2
3.7
3.3
3.7
6.6
, whichever is appropriate.
‘Std’ Speed
2.6
2.9
2.6
2.9
0.0
0.0
4.2
4.9
7.6
8.3
40MX and 42MX FPGA Families
131
121
2.9
3.4
3.9
4.4
6.4
4.0
4.4
5.6
7.2
1.0
1.0
3.8
4.4
3.9
4.3
7.8
12.7
13.8
‘–F’ Speed
3.6
4.1
3.6
4.1
0.0
0.0
5.9
6.9
10.1
10.9
4.1
4.8
5.5
6.2
9.0
5.6
6.2
7.8
1.4
1.4
5.3
6.2
5.5
6.1
79
73
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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