A3PE1500-PQG208 Actel, A3PE1500-PQG208 Datasheet - Page 152

• Manufacturer Part Number: A3PE1500-PQG208
• Description: FPGA - Field Programmable Gate Array 1500K System Gates
• Manufacturer: Actel

Specifications of A3PE1500-PQG208

• Processor Series: A3PE1500
• Core: IP Core
• Maximum Operating Frequency: 231 MHz
• Number Of Programmable I/os: 147
• Data Ram Size: 276480
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 1.5 M
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Datasheet Information
4 - 4
Revision
v2.0
(continued)
Advance v0.6
(January 2007)
Advance v0.5
(April 2006)
The "V
The "V
The "GL Globals" section was updated to include information about direct input
into quadrant clocks.
V
In Table 2-22 • Recommended Tie-Off Values for the TCK and TRST Pins, TSK
was changed to TCK in note 2. Note 3 was also updated.
Ambient was deleted from Table 3-2 • Recommended Operating Conditions.
V
Note 3 is new in Table 3-4 • Overshoot and Undershoot Limits (as measured on
quiet I/Os).
In EQ 3-2, 150 was changed to 110 and the result changed to 5.88.
Table 3-6 • Temperature and Voltage Derating Factors for Timing Delays was
updated.
Table 3-5 • Package Thermal Resistivities was updated.
Table 3-10 • Different Components Contributing to the Dynamic Power
Consumption in ProASIC3E Devices was updated.
t
3-95 • RAM512X18.
The note in Table 3-24 • I/O Input Rise Time, Fall Time, and Related I/O
Reliability was updated.
Figure 3-43 • Write Access After Write onto Same Address, Figure 3-44 • Read
Access After Write onto Same Address, and Figure 3-45 • Write Access After
Read onto Same Address are new.
Figure 3-53 • Timing Diagram was updated.
Notes were added to the package diagrams identifying if they were top or bottom
view.
The A3PE1500 "208-Pin PQFP" table is new.
The A3PE1500 "484-Pin FBGA" table is new.
The A3PE1500 "A3PE1500 Function" table is new.
In the "Packaging Tables" table, the number of I/Os for the A3PE1500 was
changed for the FG484 and FG676 packages.
B-LVDS and M-LDVS are new I/O standards added to the datasheet.
The term flow-through was changed to pass-through.
Figure 2-8 • Very-Long-Line Resources was updated.
The footnotes in Figure 2-27 • CCC/PLL Macro were updated.
The Delay Increments in the Programmable Delay Blocks specification in Figure
2-24 • ProASIC3E CCC Options.
The "SRAM and FIFO" section was updated.
The "RESET" section was updated.
WRO
JTAG
PUMP
was deleted from the "TCK Test Clock" section.
CCPLF
PUMP
programming mode was changed from "3.0 to 3.6" to "3.15 to 3.45".
and
Programming Supply Voltage" section was updated.
PLL Supply Voltage" section was updated.
t
CCKH
were
added
R e vi s i o n 9
Changes
to
Table
3-94 • RAM4K9
and
Table
3-71 to 3-
3-74 to
Page
2-50
2-50
3-80
4-18
2-28
2-21
2-51
2-51
2-51
3-74
3-23
4-24
2-24
2-25
N/A
N/A
N/A
3-5
3-5
2-8
3-2
3-2
3-5
3-8
4-4
73
ii