A3PE1500-PQG208 Actel, A3PE1500-PQG208 Datasheet - Page 57

• Manufacturer Part Number: A3PE1500-PQG208
• Description: FPGA - Field Programmable Gate Array 1500K System Gates
• Manufacturer: Actel

Specifications of A3PE1500-PQG208

• Processor Series: A3PE1500
• Core: IP Core
• Maximum Operating Frequency: 231 MHz
• Number Of Programmable I/os: 147
• Data Ram Size: 276480
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 1.5 M
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-66 • Minimum and Maximum DC Input and Output Levels
Figure 2-17 • AC Loading
Table 2-67 • AC Waveforms, Measuring Points, and Capacitive Loads
Table 2-68 • SSTL 2 Class I
SSTL2 Class I
Drive
Strength
15 mA
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
Input Low (V)
VREF – 0.2
*
Speed
Grade
Std.
–1
–2
Note:
Measuring point = Vtrip. See
For specific junction temperature and voltage supply levels, refer to
Commercial-Case Conditions: T
Worst-Case VCCI = 2.3 V, VREF = 1.25 V
SSTL2 Class I
Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support
Class I. This provides a differential amplifier input buffer and a push-pull output buffer.
Timing Characteristics
t
DOUT
0.66
0.56
0.49
Min.
–0.3 VREF – 0.2 VREF + 0.2
V
Input High (V)
VREF + 0.2
VIL
2.13
1.81
1.59
t
DP
Max.
V
Table 2-15 on page 2-19
0.04
0.04
0.03
t
DIN
Min.
V
Test Point
1.33
1.14
1.00
Measuring
t
Point* (V)
PY
VIH
1.25
J
= 70°C, Worst-Case VCC = 1.425 V,
Max.
3.6
t
V
0.43
0.36
0.32
EOUT
SSTL2
Class I
for a complete table of trip points.
25
R e v i s i o n 9
Max.
VOL
0.54
VREF (typ.) (V)
V
2.17
1.84
1.62
t
ZL
V
TT
1.25
VCCI – 0.62 15 15
50
30 pF
VOH
1.85
1.57
1.38
Min.
t
ZH
V
Table 2-6 on page 2-5
t
LZ
mA mA
I
OL
VTT (typ.) (V)
I
OH
t
1.25
HZ
ProASIC3E Flash Family FPGAs
Max.
mA
I
OSL
87
4.40
3.74
3.29
t
ZLS
1
for derating values.
Max.
I
mA
t
4.08
3.47
3.05
OSH
ZHS
C
83
LOAD
1
30
µA
10 10
(pF)
I
Units
IL
ns
ns
ns
2
µA
2- 45
I
IH
2