A3PE1500-PQG208 Actel, A3PE1500-PQG208 Datasheet - Page 36

• Manufacturer Part Number: A3PE1500-PQG208
• Description: FPGA - Field Programmable Gate Array 1500K System Gates
• Manufacturer: Actel

Specifications of A3PE1500-PQG208

• Processor Series: A3PE1500
• Core: IP Core
• Maximum Operating Frequency: 231 MHz
• Number Of Programmable I/os: 147
• Data Ram Size: 276480
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 1.5 M
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ProASIC3E DC and Switching Characteristics
2- 24
Table 2-22 • Duration of Short Circuit Event before Failure
Table 2-23 • Schmitt Trigger Input Hysteresis
Table 2-24 • I/O Input Rise Time, Fall Time, and Related I/O Reliability*
Input Buffer
LVTTL/LVCMOS
(Schmitt trigger disabled)
LVTTL/LVCMOS
(Schmitt trigger enabled)
HSTL/SSTL/GTL
LVDS/B-LVDS/M-LVDS/
LVPECL
*
Temperature
100°C
110°C
Input Buffer Configuration
3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode)
2.5 V LVCMOS (Schmitt trigger mode)
1.8 V LVCMOS (Schmitt trigger mode)
1.5 V LVCMOS (Schmitt trigger mode)
For clock signals and similar edge-generating signals, refer to the "ProASIC3/E SSO and Pin
Placement Guidelines" chapter of the
rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, then the rise
time and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall
times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity
evaluation/characterization of the system to ensure that there is no excessive noise coupling into input
signals.
Hysteresis Voltage Value (typ.) for Schmitt Mode Input Buffers
Input Rise/Fall Time
No requirement
No requirement
No requirement
No requirement
(min.)
ProASIC3E FPGA Fabric User’s
R e visio n 9
No requirement, but input noise
voltage
hysteresis.
Input Rise/Fall Time (max.)
Time before Failure
cannot
10 ns *
10 ns *
10 ns *
6 months
3 months
exceed
Guide. The maximum input
Hysteresis Value (typ.)
Schmitt
240 mV
140 mV
80 mV
60 mV
Reliability
20 years
20 years
10 years
10 years
(110°C)
(110°C)
(100°C)
(100°C)