APA075-PQG208 Actel, APA075-PQG208 Datasheet - Page 38

• Manufacturer Part Number: APA075-PQG208
• Description: FPGA - Field Programmable Gate Array 75K System Gates
• Manufacturer: Actel

Specifications of APA075-PQG208

• Processor Series: APA075
• Core: IP Core
• Maximum Operating Frequency: 150 MHz
• Number Of Programmable I/os: 158
• Data Ram Size: 27648
• Supply Voltage (max): 2.7 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: APA-Eval-Kit, APA-Eval-BRD1, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.3 V
• Number Of Gates: 75 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Calculating Typical Power Dissipation
ProASIC
of both the number of tiles utilized and the system speed. Power dissipation can be calculated using the following
formula:
Total Power Consumption—P
where:
Global Clock Contribution—P
P
for R < 15000 the model is: (P1 + (P2*R) – (P7*R2)) * Fs (lightly-loaded clock trees)
for R > 15000 the model is: (P10 + P11*R) * Fs (heavily-loaded clock trees)
where:
Storage-Tile Contribution—P
P
where:
2 -2 8
clock
storage
ProASIC
P
P
P
P
P10 =
P11 =
P5
ms =
Fs
P1
P2
P7
total
, the clock component of power dissipation, is given by the piece-wise model:
storage
dc
ac
Fs
R
, the storage-tile (Register) component of AC power dissipation, is given by
PLUS
=
=
= P
=
=
=
=
=
PLUS
=
=
= P5 * ms * Fs
dc
100 µW/MHz is the basic power consumption of the clock tree per MHz of the clock
1.3 µW/MHz is the incremental power consumption of the clock tree per storage tile – also per MHz of the
clock
0.00003 µW/MHz is a correction factor for partially-loaded clock trees
device power is calculated with both a static and an active component. The active component is a function
7 mW for the APA075
8 mW for the APA150
11 mW for the APA300
12 mW for the APA450
12 mW for the APA600
13 mW for the APA750
19 mW for the APA1000
P
P
6850 µW/MHz is the basic power consumption of the clock tree per MHz of the clock
0.4 µW/MHz is the incremental power consumption of the clock tree per storage tile – also per MHz of
the clock
the number of storage tiles clocked by this clock
the clock frequency
dc
clock
1.1 µW/MHz is the average power consumption of a storage tile per MHz of its output toggling rate.
The maximum output toggling rate is Fs/2.
the number of storage tiles (Register) switching during each Fs cycle
the clock frequency
Flash Family FPGAs
+ P
includes the static components of P
ac
+ P
storage
+ P
storage
logic
clock
total
+ P
outputs
+ P
inputs
VDDP
+ P
pll
+ P
v5.9
+ P
VDD
memory
+ P
AVDD