APA075-PQG208 Actel, APA075-PQG208 Datasheet - Page 79

• Manufacturer Part Number: APA075-PQG208
• Description: FPGA - Field Programmable Gate Array 75K System Gates
• Manufacturer: Actel

Specifications of APA075-PQG208

• Processor Series: APA075
• Core: IP Core
• Maximum Operating Frequency: 150 MHz
• Number Of Programmable I/os: 158
• Data Ram Size: 27648
• Supply Voltage (max): 2.7 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: APA-Eval-Kit, APA-Eval-BRD1, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.3 V
• Number Of Gates: 75 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent)
Note: The plot shows the normal operation status.
Figure 2-42 • Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent)
Table 2-65 • T
Symbol t
CCYC
CMH
CML
ECBA
FCBA
ECBH, FCBH,
THCBH
OCA
OCH
RDCH
RDCS
RPCA
RPCH
HCBA
Note: *At fast cycles, ECBA and FCBA = MAX (7.5 ns – CMH), 3.0 ns.
xxx
T
J
J
= 0°C to 110°C; V
= –55°C to 150°C, V
Clock high phase
Clock low phase
FULL ↓ access from RCLKS ↓
Old EMPTY, FULL, EQTH, & GETH valid hold
time from RCLKS ↓
Old DO valid from RCLKS ↑
RDB hold from RCLKS ↑
RDB setup to RCLKS ↑
Old RPE valid from RCLKS ↑
Cycle time
New EMPTY access from RCLKS ↓
New DO access from RCLKS ↑
New RPE access from RCLKS ↑
EQTH or GETH access from RCLKS ↓
EQTH, GETH
Description
DD
RDATA
EMPTY
RCLK
DD
FULL
= 2.3 V to 2.7 V for Commercial/Industrial
RDB
RPE
= 2.3 V to 2.7 V for Military/MIL-STD-883
t RDCS
t RDCH
Old Data Out
t RPCH
t OCH
t OCA
t RPCA
Cycle Start
t CMH
Min.
3.0*
3.0*
7.5
3.0
3.0
7.5
0.5
1.0
9.5
4.5
v5.9
t CCYC
New Valid Data Out (Empty Inhibits Read)
t THCBH
Max.
1.0
3.0
3.0
t HCBA
t CML
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t ECBH , t FCBH
t ECBA , t FCBA
Empty/full/thresh are invalid from the end
of hold until the new access is complete
ProASIC
PLUS
Notes
Flash Family FPGAs
2-69