LIS331HH STMicroelectronics, LIS331HH Datasheet
LIS331HH
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LIS331HH Summary of contents
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... Thresholds and timing of interrupt generators are programmable by the end user on the fly. The LIS331HH is available in small thin plastic land grid array package (LGA) and it is guaranteed to operate over an extended temperature range from -40 °C to +85 °C. ...
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... I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.1 5.2 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.1 5.2.2 5.2.3 2/37 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 I2C - inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Sleep to wake- I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SPI read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Doc ID 16366 Rev 1 LIS331HH ...
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... LIS331HH 6 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 CTRL_REG1 (20h 7.2 CTRL_REG2 (21h 7.3 CTRL_REG3 [Interrupt CTRL register] (22h 7.4 CTRL_REG4 (23h 7.5 CTRL_REG5 (24h 7.6 HP_FILTER_RESET (25h 7.7 REFERENCE (26h 7.8 STATUS_REG (27h 7.9 OUT_X_L (28h), OUT_X_H (29 7.10 OUT_Y_L (2Ah), OUT_Y_H (2Bh ...
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... INT1_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 38. Interrupt 1 source configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 39. INT1_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 40. INT1_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 41. INT1_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 42. INT1_THS description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 43. INT1_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 44. INT2_DURATION description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 45. INT2_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 46. INT2_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 47. Interrupt mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 48. INT2_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4/37 Doc ID 16366 Rev 1 LIS331HH ...
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... LIS331HH Table 49. INT2_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 50. INT2_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 51. INT2_THS description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 52. INT2_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 53. INT2_DURATION description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 54. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Doc ID 16366 Rev 1 List of tables 5/37 ...
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... Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. SPI slave timing diagram (2 Figure 4. I2C slave timing diagram ( Figure 5. LIS331HH electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 6. Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 7. SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 8. Multiple bytes SPI read protocol (2 bytes example Figure 9. SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 10 ...
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... LIS331HH 1 Block diagram and pin description 1.1 Block diagram Figure 1. Block diagram a SELF TEST 1.2 Pin description Figure 2. Pin connection X Y (TOP VIEW) DIRECTION OF THE DETECTABLE ACCELERATIONS X+ Y+ CHARGE AMPLIFIER Z+ A/D MUX CONVERTER TRIMMING REFERENCE CIRCUITS Z 1 Doc ID 16366 Rev 1 Block diagram and pin description ...
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... C less significant bit of the device address (SA0) SPI enable C/SPI mode selection (1: I INT 2 Inertial interrupt 2 Reserved Connect to GND INT 1 Inertial interrupt 1 GND 0 V supply GND 0 V supply Vdd Power supply Reserved Connect to Vdd GND 0 V supply Doc ID 16366 Rev 1 LIS331HH Function 2 C mode; 0: SPI enabled) ...
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... LIS331HH 2 Mechanical and electrical specifications 2.1 Mechanical characteristics Table 3. Mechanical characteristics @ Vdd = 2 °C unless otherwise noted Symbol Parameter FS Measurement range So Sensitivity Sensitivity change vs TCSo temperature g Typical zero- level offset TyOff (4),(5) accuracy g Zero- level change vs TCOff temperature An Acceleration noise density Self-test ...
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... PM bit set to 011 PM bit set to 100 PM bit set to 101 PM bit set to 110 ODR = 100 Hz Doc ID 16366 Rev 1 (1) (2) Min. Typ. Max. 2.16 2.5 3.6 1.71 Vdd+0.1 250 10 1 0.2*Vdd_IO 0.1*Vdd_IO 50 100 400 1000 0 ODR/2 1/ODR+1ms -40 +85 LIS331HH Unit V V µA µA µ ° C ...
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... LIS331HH 2.3 Communication interface characteristics 2.3.1 SPI - serial peripheral interface Subject to general operating conditions for Vdd and Top. Table 5. SPI slave timing values Symbol tc(SPC) SPI clock cycle fc(SPC) SPI clock frequency tsu(CS) CS setup time th(CS) CS hold time tsu(SI) SDI input setup time ...
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... I C standard mode Min Max 0 100 4.7 4.0 250 0 3.45 1000 300 4 4.7 4 4.7 ( h(SDA) su(SDA r(SCL) f(SCL) Doc ID 16366 Rev 1 LIS331HH 2 ( fast mode Unit Min Max 0 400 KHz 1.3 µs 0.6 100 ns 0.01 0.9 µ 300 300 20 + 0.1C b 0.6 0.6 µ ...
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... LIS331HH 2.4 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability ...
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... The “sleep to wake-up” function, in conjunction with low-power mode, allows to further reduce the system power consumption and develop new smart applications. LIS331HH may be set in a low-power operating mode, characterized by lower date rates refreshments. In this way the device, even if sleeping, keep on sensing acceleration and generating interrupt requests. When the “ ...
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... The acceleration data may be accessed through an I device particularly suitable for direct interfacing with a microcontroller. The LIS331HH features a Data-Ready signal (RDY) which indicates when a new set of measured acceleration data is available thus simplifying data synchronization in the digital system that uses the device. ...
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... Application hints 4 Application hints Figure 5. LIS331HH electrical connection Vdd Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO The device core is supplied through Vdd line while the I/O pads are supplied through Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF Aluminum) should be placed as near as possible to the pin 14 of the device (common design practice) ...
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... DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines are connected to Vdd_IO through a pull-up resistor embedded inside the LIS331HH. When the bus is free both the lines are high. 2 The I C interface is compliant with fast mode (400 kHz) I normal mode ...
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... If they match, the device considers itself addressed by the Master. The Slave ADdress (SAD) associated to the LIS331HH is 001100xb. SDO/SA0 pad can be used to modify less significant bit of the device address. If SA0 pad is connected to voltage supply, LSb is ‘1’ (address 0011001b) else if SA0 pad is connected to ground, LSb value is ‘ ...
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... In the presented communication format MAK is Master acknowledge and NMAK is No Master Acknowledge. 5.2 SPI bus interface The LIS331HH SPI is a bus slave. The SPI allows to write and read the registers of the device. The Serial Interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO. SAD + W ...
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... AD5 AD4 AD3 AD2 AD1 AD0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 RW MS AD5 AD4 AD3 AD2 AD1 AD0 Doc ID 16366 Rev 1 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 LIS331HH ...
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... LIS331HH The SPI Read command is performed with 16 clock pulses. Multiple byte read command is performed adding blocks of 8 clock pulses at the previous one. bit 0: READ bit. The value is 1. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple reading. ...
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... DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 AD5 AD4 AD3 AD2 AD1 AD0 RW MS AD5 AD4 AD3 AD2 AD1 AD0 Doc ID 16366 Rev 1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 LIS331HH ...
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... LIS331HH 6 Register mapping The table given below provides a listing of the 8 bit registers embedded in the device and the related addresses: Table 15. Register address map Name Reserved (do not modify) CTRL_REG1 CTRL_REG2 CTRL_REG3 CTRL_REG4 CTRL_REG5 HP_FILTER_RESET REFERENCE STATUS_REG OUT_X_L OUT_X_H OUT_Y_L OUT_Y_H OUT_Z_L OUT_Z_H ...
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... Power mode and low-power output data rate configurations PM2 PM1 24/37 PM0 DR1 Table 19) PM0 Power mode selection 0 0 Power-down 0 1 Normal mode 1 0 Low-power 1 1 Low-power 0 0 Low-power Doc ID 16366 Rev 1 DR0 Zen Yen Table 18) Table 18 Table 19 Output data rate [Hz] ODR -- ODR 0 LIS331HH Xen shows all LP ...
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... LIS331HH Table 18. Power mode and low-power output data rate configurations (continued) PM2 PM1 1 1 Table 19. Normal-mode output data rate configurations and low-pass cut-off frequencies DR1 7.2 CTRL_REG2 (21h) Table 20. CTRL_REG2 register BOOT HPM1 Table 21. CTRL_REG2 description Reboot memory content. Default value: 0 BOOT (0: normal mode ...
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... HPc --------------------- - f t ⋅ 6 HPc f [Hz] f [Hz Data rate = 100 0.5 1 0.25 0.5 0.125 0.25 LIR2 I2_CFG1 I2_CFG0 Doc ID 16366 Rev 1 High-pass filter mode f ⎞ s ⋅ ------ ⎠ 2π f [Hz Data rate = 400 Hz Data rate = 1000 LIR1 I1_CFG1 LIS331HH [Hz 2.5 I1_CFG0 ...
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... LIS331HH Table 25. CTRL_REG3 description (continued) Latch interrupt request on INT2_SRC register, with INT2_SRC register cleared by reading INT2_SRC itself. Default value: 0. LIR2 (0: interrupt request not latched; 1: interrupt request latched) Data signal on INT 2 pad control bits. Default value: 00. I2_CFG1, I2_CFG0 (see table below) Latch interrupt request on INT1_SRC register, with INT1_SRC register cleared by reading INT1_SRC register ...
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... This allows to overcome the settling time of the high pass filter. 7.7 REFERENCE (26h) Table 32. REFERENCE register Ref7 Ref6 28/ TurnOn0 0 Sleep to wake function is disabled Turned on: The device is in low power mode (ODR is defined in 1 Ref5 Ref4 Doc ID 16366 Rev TurnOn1 Sleep to wake status CTRL_REG1) Ref3 Ref2 Ref1 LIS331HH TurnOn0 Ref0 ...
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... LIS331HH Table 33. REFERENCE description Ref7 - Ref0 Reference value for high-pass filter. Default value: 00h. This register sets the acceleration value taken as a reference for the high-pass filter output. When filter is turned on (at least one of FDS, HPen2, or HPen1 bit is equal to ‘1’) and HPM bits are set to “ ...
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... Enable interrupt generation on X low event. Default value: 0 XLIE (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Configuration register for Interrupt 1 source. 30/37 ZHIE ZLIE Table 38) Table 38) Doc ID 16366 Rev 1 YHIE YLIE XHIE LIS331HH XLIE ...
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... LIS331HH Table 38. Interrupt 1 source configurations AOI 7.13 INT1_SRC (31h) Table 39. INT1_SRC register 0 IA Table 40. INT1_SRC description Interrupt active. Default value (0: no interrupt has been generated; 1: one or more interrupts have been generated) Z high. Default value (0: no interrupt High event has occurred) Z low. Default value (0: no interrupt ...
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... Enable interrupt generation on Y low event. Default value: 0 YLIE (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) 32/37 Interrupt 1 threshold. Default value: 000 0000 D5 D4 Duration value. Default value: 000 0000 ZHIE ZLIE Doc ID 16366 Rev YHIE YLIE XHIE LIS331HH D0 XLIE ...
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... LIS331HH Table 46. INT2_CFG description Enable interrupt generation on X high event. Default value: 0 XHIE (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on X low event. Default value: 0 XLIE (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Configuration register for Interrupt 2 source ...
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... bits set the minimum duration of the Interrupt 2 event to be recognized. Duration time steps and maximum values depend on the ODR chosen. 34/37 THS5 THS4 Interrupt 1 threshold. Default value: 000 0000 D5 D4 Duration value. Default value: 000 0000 Doc ID 16366 Rev 1 THS3 THS2 THS1 LIS331HH THS0 D0 ...
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... LIS331HH 8 Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK trademark. Figure 12. LGA16: Mechanical data and package dimensions Ref. Min. ...
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... Revision history 9 Revision history Table 54. Document revision history Date 05-Oct-2009 36/37 Revision 1 Initial release Doc ID 16366 Rev 1 LIS331HH Changes ...
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... LIS331HH Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...