PCF8564ACX9/B/1,02 NXP Semiconductors, PCF8564ACX9/B/1,02 Datasheet - Page 21

• Manufacturer Part Number: PCF8564ACX9/B/1,02
• Description: IC RTC/CALENDAR
• Manufacturer: NXP Semiconductors
• Type: Clock/Calendar/Alarmr

Specifications of PCF8564ACX9/B/1,02

• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: Die
• Function: Serial Clock, Alarm, Calendar, Timer, Timer Interrupt
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1 V
• Mounting Style: SMD/SMT
• Rtc Bus Interface: I2C
• Supply Current: 1700 nA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed
• Other names: 568-6424-2; PCF8564ACX9/B/1,02

NXP Semiconductors
9. Characteristics of the I
PCF8564A
Product data sheet
9.1 Bit transfer
9.2 START and STOP conditions
9.3 System configuration
The I
The two lines are a Serial Data Line (SDA) and a Serial Clock Line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only
when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH, is defined as the START condition (S).
A LOW-to-HIGH transition of the data line, while the clock is HIGH, is defined as the
STOP condition (P), see
A device generating a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message is the master; and the devices which are
controlled by the master are the slaves (see
Fig 12. Bit transfer
Fig 13. Definition of START and STOP conditions
2
C-bus is for bidirectional, two-line communication between different ICs or modules.
SDA
SCL
START condition
All information provided in this document is subject to legal disclaimers.
2
SDA
SCL
C-bus
S
Rev. 02 — 30 September 2010
Figure
13.
data valid
data line
stable;
Figure
Figure
allowed
change
of data
12).
14).
Real time clock and calendar
STOP condition
PCF8564A
mbc621
P
© NXP B.V. 2010. All rights reserved.
mbc622
SDA
SCL
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