LPC2146FBD64,557 NXP Semiconductors, LPC2146FBD64,557 Datasheet - Page 22
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LPC2146FBD64,557
Manufacturer Part Number
LPC2146FBD64,557
Description
IC ARM7 MCU FLASH 256K 64LQFP
Manufacturer
NXP Semiconductors
Series
LPC2100r
Datasheet
1.LPC2141FBD64151.pdf
(40 pages)
Specifications of LPC2146FBD64,557
Core Processor
ARM7
Core Size
16/32-Bit
Speed
60MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 14x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2146FBD64,557
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
LPC2141_42_44_46_48_4
Product data sheet
6.19.1 Crystal oscillator
6.19.2 PLL
6.19.3 Reset and wake-up timer
6.19 System control
On-chip integrated oscillator operates with external crystal in range of 1 MHz to 25 MHz.
The oscillator output frequency is called f
referred to as CCLK for purposes of rate equations, etc. f
unless the PLL is running and connected. Refer to
information.
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled
Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the
multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper
frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so
there is an additional divider in the loop to keep the CCO within its frequency range while
the PLL is providing the desired output frequency. The output divider may be set to divide
by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,
it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and
bypassed following a chip reset and may be enabled by software. The program must
configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a
clock source. The PLL settling time is 100 s.
Reset has two sources on the LPC2141/42/44/46/48: the RESET pin and watchdog reset.
The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of
chip reset by any source starts the Wake-up Timer (see Wake-up Timer description
below), causing the internal chip reset to remain asserted until the external reset is
de-asserted, the oscillator is running, a fixed number of clocks have passed, and the
on-chip flash controller has completed its initialization.
When the internal reset is removed, the processor begins executing at address 0, which is
the reset vector. At that point, all of the processor and peripheral registers have been
initialized to predetermined values.
The Wake-up Timer ensures that the oscillator and other analog functions required for
chip operation are fully functional before the processor is allowed to execute instructions.
This is important at power on, all types of reset, and whenever any of the aforementioned
functions are turned off for any reason. Since the oscillator and other functions are turned
off during Power-down mode, any wake-up of the processor from Power-down mode
makes use of the Wake-up Timer.
•
•
•
Match register updates are synchronized with pulse outputs to prevent generation of
erroneous pulses. Software must ‘release’ new match values before they can become
effective.
May be used as a standard timer if the PWM mode is not enabled.
A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
Rev. 04 — 17 November 2008
osc
and the ARM processor clock frequency is
LPC2141/42/44/46/48
Single-chip 16-bit/32-bit microcontrollers
Section 6.19.2 “PLL”
osc
and CCLK are the same value
© NXP B.V. 2008. All rights reserved.
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