SI5110-H-BL Silicon Laboratories Inc, SI5110-H-BL Datasheet
SI5110-H-BL
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SI5110-H-BL Summary of contents
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... To simplify BER optimization in long haul applications, programmable slicing and sample phase adjustment are supported. The Si5110 operates from a single 1.8 V supply over the industrial temperature range (– °C). Functional Block Diagram ...
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Rev. 1.4 ...
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... Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 13. Transmit Differential Output Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 14. Internal Pullups and Pulldowns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 15. Power Supply Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 16. Si5110 Pinout: 99 BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 17. Pin Descriptions: Si5110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 18. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 19. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 20. 11x11 mm 99L CBGA Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Rev ...
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Detailed Block Diagram PHASEADJ SLICEMODE LTR SLICELVL Lim iting CDR RXDIN Amp LOSLVL LOS RXAMPMON FIFOERR FIFORST TXSQLCH TXDOUT TXCLKDSBL TXCLKOUT TXLOL TXMSBSEL BWSEL[1:0] 4 RXLOL LOS 1:4 DE- MUX 4:1 8:4 MUX MUX ...
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... Table 1. Recommended Operating Conditions Parameter Ambient Temperature LVTTL I/O Supply Voltage Si5110 Supply Voltage *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. V ...
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All Differential IOs Table 2. DC Characteristics (V = 1.8 V ±5 – ° Parameter Supply Current Power Dissipation Voltage Reference (VREF) Common Mode Input Voltage (RXDIN) Differential Input ...
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... I SC(+) 1.8–3.3 V IL2 DDIO 1.8–3.3 V 0.65 V IH2 DDIO 1.8–3.3 V OL2 DDIO = V V 1.8–3 DDIO OH2 DDIO mV (single-ended) PP Rev. 1.4 Si5110 Min Typ Max Unit mV 550 650 800 1.125 1.2 1.275 110 130 — 100 — — –8 – ...
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Table 3. AC Characteristics (RXDIN, RXDOUT, RXCLK1, RXCLK2 1.8 V ±5 – ° Parameter Input Data Rate (RXDIN) Output Clock Frequency (RXCLK1) Output Clock Frequency (RXCLK2) Duty ...
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... Symbol Test Condition 10–600 Hz TOL(PP 0.6–6 kHz f = 6–100 kHz f = 100 kHz–1 MHz f = 1–20 MHz REFRATE = 1 FREQ REFRATE = 0 RC DUTY RC TOL LOL LOCK Rev. 1.4 Si5110 Min Typ Max Unit 2.41 — 2.7 GHz — — –42 — ...
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Table 6. AC Characteristics (Transmitter Clock Multiplier 1.8 V ±5 – ° Parameter Jitter Transfer Bandwidth OCH48: 2.48832 Gbps FEC: 2.666676 Gbps Jitter Transfer Peaking Acquisition Time ...
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... Thermal Resistance Junction to Ambient Symbol Value V –0 –0.5 to 4.0 DDIO V 5 DIF V –0 0.3) DIF DD V 2.4 DIF V 5 DIF ±50 T –55 to 150 JCT T –55 to 150 STG 1 2 Symbol Test Condition ϕ Still Air JA Rev. 1.4 Si5110 Unit ° C ° Value Unit 31 °C/W 11 ...
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... TXCLK4IN± Loss-of-Signal Data Slice Level Set Level Set Note* See 15. "Power Supply Filtering" on page 20. 12 LVTTL Control Inputs RXAMPMON FIFOERR TXLOL RXLOL LOS Si5110 RXDOUT[3:0]± RXCLK1± RXCLK2± TXDOUT± TXCLKOUT± TXCLK4OUT± VREF 3.091 k 3.091 VDD Power ...
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... RXDIN PP The receiver signal amplitude monitoring circuit is also used in the generation of the loss-of-signal alarm (LOS). 5.2.2. Loss-of-Signal Alarm (LOS) The Si5110 can be configured to activate a loss-of- signal alarm output (LOS) when the RXDIN input OC-48/STM-16 amplitude drops below a programmable threshold level. An appropriate level of hysteresis prevents unnecessary ...
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... In applications introduced by the transmission medium, it may be desirable to recover data by sampling at a point that is not at the center of the data eye. The Si5110 provides a sample phase adjustment adjustment of the CDR sampling phase across the NRZ data period. When sample phase adjustment is enabled, the sampling instant used for data recovery can be moved over a range of approximately ± ...
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... RXDOUT[3:0], aligned with the rising edge of RXCLK1. 5.4.1. Serial Input to Parallel Output Relationship The Si5110 provides the capability to select the order in which the received serial data is mapped to the parallel output bus RXDOUT[3:0]. The mapping of the receive bits to the output data word is controlled by the RXMSBSEL input ...
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350 300 250 200 150 100 0.05 Figure 5. Typical LOSLVL Transfer Curve, Proportional Slice Mode (SLICEMODE = -20 -40 -60 0.35 Figure 6. Typical SLICELVL Transfer ...
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... Figure 7. Typical SLICELVL Transfer Curve, Proportional Slice Mode (SLICEMODE = -10 -20 -30 -40 0.2 0.3 Figure 8. Typical PHASEADJ Transfer Curve 0.4 0.45 0.5 0.55 0.6 0.65 SLICELVL (V) PHASEADJ Transfer Curve 0.4 0.5 0.6 PHASEADJ (Volts) Rev. 1.4 Si5110 0.7 0.75 0.7 0.8 17 ...
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... The TXLOL signal will also be asserted during the transmit CMU frequency calibration. Calibration is performed automatically when the Si5110 is powered on, when a valid clock signal is detected on the selected reference clock input following margin to ...
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... TXLOL transitions from low to high). 6.2.2. Parallel Input To Serial Output Relationship The Si5110 provides the capability to select the order in which the data received on the parallel input bus TXDIN[3:0] is transmitted serially on the high-speed serial data output TXDOUT. Data on the parallel bus will be transmitted MSB first or LSB first depending on the setting of the TXMSBSEL input ...
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... CDR locks to the data input, the RXLOL signal is deasserted (driven high). 20 12. Reset The Si5110 is reset by holding the RESET pin low for at least 1 µ s. When RESET is asserted, the input FIFO pointers are reset and the digital control circuitry is initialized. reduce ...
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... Figure 9. CML Output Driver Termination (TXCLKOUT, TXDOUT) 0.1 μF RXDIN+ RXDIN– 0.1 μF Figure 10. Receiver Differential Input Circuitry Rev. 1.4 VDD 50 Ω Ω Ω 50 Ω VDD 1.5 V 150Ω 150Ω + – 75Ω 75Ω Si5110 21 ...
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100 Ω Figure 11. LVDS Differential Input Circuitry Out + ESD Figure 12. LVDS Driver Termination (RXDOUT, TXCLK4OUT) 22 ESD 5 kΩ 5 kΩ ESD Common Mode Adjust Circuit 6.5 mA ...
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... GND REFCLK– GND GND TXDIN[2]+ TXDIN[3]+ LPTM TXDIN[2]– TXDIN[3]– LLBK TXDIN[0]+ TXDIN[1]+ TXCLKDSBL TXDIN[0]– TXDIN[1]– TXCLK4IN+ Figure 13. Si5110 Pin Configuration (Bottom View RXCLK2– RSVD_GND RXSQLCH RXREXT RXCLK1– RSVD_GND RXAMPMON VREF SLICEMODE RSVD_GND LTR VDD ...
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... F TXCLKOUT– GND REFRATE G GND VDDIO RSVD_GND H TXDOUT+ GND BWSEL1 J TXDOUT– GND RSVD_GND K GND TXREXT RSVD_GND Figure 14. Si5110 Pin Configuration (Transparent Top View RXREXT RXSQLCH RSVD_GND RXCLK2– VREF RXAMPMON RSVD_GND RXCLK1– LTR RSVD_GND SLICEMODE RXCLK2DSBL VDD VDD VDD ...
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... Pin Descriptions: Si5110 Pin Name Number(s) H3 BWSEL1 H6 BWSEL0 H7 DLBK J5 FIFOERR H5 FIFORST B2, C2, D1, GND GND E2, E7–9, F2, F7–9, G1, H2, J2 LLBK D2 LOS B3 LOSLVL I/O Signal Level I LVTTL Transmit DSPLL Bandwidth Select. The inputs select loop bandwidth of the Transmit Clock Multiplier DSPLL as listed in Table 6. ...
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... Si5110 transmit CMU, which is used to generate the high-speed transmit clock TXCLKOUT. The reference clock is also used by the Si5110 receiver CDR to cen- ter the PLL during lock acquisition, and as a reference for determination of the receiver lock status. ...
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... Si5110 transmit CMU, which is used to generate the high-speed transmit clock TXCLKOUT. The reference clock is also used by the Si5110 receiver CDR to cen- ter the PLL during lock acquisition, and as a reference for determination of the receiver lock status. ...
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Pin Name Number(s) A8 RXCLK2+, A7 RXCLK2– C8 RXCLK2DIV D3 RXCLK1DSBL C7 RXCLK2DSBL B1, C1 RXDIN+, RXDIN– C9 RXDOUT3+ D9 RXDOUT3– C10 RXDOUT2+ D10 RXDOUT2– A9 RXDOUT1+ B9 RXDOUT1– A10 RXDOUT0+ B10 RXDOUT0– C3 RXLOL ...
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... Divided Down Transmit Clock Output. This clock output is generated by dividing down the high-speed output clock, TXCLKOUT factor intended for use in counter clocking schemes that transfer data between the system framer and the Si5110. (See REFSEL and REFRATE descriptions.) Rev. 1.4 Si5110 Description 29 ...
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Pin Name Number(s) J8 TXCLKDSBL E1 TXCLKOUT+, F1 TXCLKOUT– G9 TXDIN3+, H9 TXDIN3– G10 TXDIN2+, H10 TXDIN2– J9 TXDIN1+, K9 TXDIN1– J10 TXDIN0+, K10 TXDIN0– H1 TXDOUT+, J1 TXDOUT– K4 TXLOL H4 TXMSBSEL K3 TXREXT ...
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... O Voltage Ref Voltage Reference. The Si5110 provides an output voltage reference that can be used by an external circuit to set the LOS threshold, slicing level, or sampling phase adjustment. The equivalent resistance between this pin and GND should not be less than 10 k Ω . The reference voltage is nominally 1 ...
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... 18. Ordering Guide Part Number Si5110-G-BC Si5110-H-BL Si5110-H-GL 32 Package Temperature Range 99-Ball CBGA – °C (Prior Revision) RoHS-5 99-Ball PBGA – °C (Current Revision) RoHS-5 99-Ball PBGA – °C (Current Revision) RoHS-6 Rev. 1.4 ...
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... Package Outline Figure 15 illustrates the package details for the Si5110. Table 9 lists the values for the dimensions shown in the illustration. Figure 15. 99-Ball Plastic Ball Grid Array (PBGA) Table 9. Package Diagram Dimensions (mm) Symbol Min Nom A 1.22 1.39 A1 0.40 0.50 A2 0.32 0.36 A3 0.46 ...
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20. 11x11 mm 99L PBGA Recommended PCB Layout Symbol Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land ...
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... OCUMENT HANGE IST Revision 0.53 to Revision 1.0 Update Si5110 1. "Detailed Block Diagram" on page 4 to clarify control RXAMPMON and CMU timing sources. Figure 1 on page 5; clarified the measurement of VICM, and VOCM Updated Table 2 on page 6. Updated Table 3 on page 8. Updated Table 4 on page 9. ...
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