SI5110-H-BL Silicon Laboratories Inc, SI5110-H-BL Datasheet - Page 35

• Manufacturer Part Number: SI5110-H-BL
• Description: IC TXRX SONET/SDH LP HS 99-PBGA
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5110-H-BL

• Product: PHY
• Supply Voltage (max): 1.89 V, 3.47 V
• Supply Voltage (min): 1.71 V
• Supply Current: 0.7 A
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 20 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 1300 mW
• Number Of Channels: 1
• Package / Case: BGA-99
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

D
Revision 0.53 to Revision 1.0
Revision 1.0 to Revision 1.1
Revision 1.1 to Revision 1.2
Revision 1.2 to Revision 1.3
OCUMENT
Update Si5110 1. "Detailed Block Diagram" on page
4 to clarify control RXAMPMON and CMU timing
sources.
Figure 1 on page 5; clarified the measurement of
VICM, and VOCM
Updated Table 2 on page 6.
Updated Table 3 on page 8.
Updated Table 4 on page 9.
Updated Table 5 on page 9.
Updated Table 6 on page 10.
Updated Table 7 on page 11.
Update 3. "Typical Application Schematic" on page
12 to show connection between FIFORSTb and
FIFOERRb.
Updated RXAMPMON description and equation in
5.2.1. "Receiver Signal Amplitude Monitoring" on
page 13.
Updated LOSLVL equations, and related figures
(Figure 4 and Figure 5 on page 16).
Clarified 5.3. "Clock and Data Recovery (CDR)" on
page 14.
Added Figure 9, “CML Output Driver Termination
(TXCLKOUT, TXDOUT),” on page 21 and Figure 10,
“Receiver Differential Input Circuitry,” on page 21.
Updated RXAMPMON, RXDIN, REFCLK, and
TXCLK4IN pin descriptions in 17. "Pin Descriptions:
Si5110" on page 25.
Updated 19. "Package Outline" on page 33.
Updated Table 2, “DC Characteristics,” on page 6.
Updated Table 9, “Package Diagram Dimensions
(mm),” on page 33.
Updated LVDS Input Impedance in Table 2, “DC
Characteristics,” on page 6.
Added test condition for Acquisition Time in Table 6,
“AC Characteristics (Transmitter Clock Multiplier)1,”
on page 10.
Updated 19. "Package Outline" on page 33.
Updated chip graphic on page 1.
Corrected "18. Ordering Guide" on page 32.
C
HANGE
L
IST
Rev. 1.4
Revision 1.3 to Revision 1.4
Updated "18. Ordering Guide" on page 32.
Updated "19. Package Outline" on page 33.
Updated "20. 11x11 mm 99L PBGA Recommended
PCB Layout" on page 34.
Si5110
35