NX3L1G384GW,125 NXP Semiconductors, NX3L1G384GW,125 Datasheet
NX3L1G384GW,125
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NX3L1G384GW,125 Summary of contents
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NX3L1G384 Low-ohmic single-pole single-throw analog switch Rev. 4 — 7 January 2011 1. General description The NX3L1G384 is a low-ohmic single-pole single-throw analog switch. It has two input/output terminals (Y and Z) and an active LOW enable input pin (E). ...
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... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name −40 °C to +125 °C NX3L1G384GW −40 °C to +125 °C NX3L1G384GM 5. Marking [1] Table 2. Marking codes Type number NX3L1G384GW NX3L1G384GM [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. ...
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... NXP Semiconductors 7.2 Pin description Table 3. Pin description Symbol Pin SOT353 GND n. Functional description [1] Table 4. Function table Input [ HIGH voltage level LOW voltage level. 9. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...
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... NXP Semiconductors 10. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V switch voltage SW T ambient temperature amb Δt/ΔV input transition rise and fall rate [1] To avoid sinking GND current from of terminal Z when switch current flows in terminal Y, the voltage drop across the bidirectional switch must not exceed 0 ...
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... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground 0 V). Symbol Parameter Conditions C input I capacitance C OFF-state S(OFF) capacitance C ON-state S(ON) capacitance 11.1 Test circuits GND V I − Fig 5. Test circuit for measuring OFF-state leakage current 11.2 ON resistance Table 8 ...
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... NXP Semiconductors Table 8. ON resistance …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Symbol Parameter Conditions R ON resistance V = GND to V ON(flat) I (flatness 100 [1] Typical values are measured at T [2] Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical V temperature ...
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... NXP Semiconductors 1 (Ω) 1.2 0.8 0 125 °C. (1) T amb = 85 °C. (2) T amb = 25 °C. (3) T amb = −40 °C. (4) T amb Fig 9. ON resistance as a function of input voltage 1 1 (Ω) 0.8 0.6 0.4 0 125 °C. (1) T amb = 85 °C. (2) T amb = 25 °C. (3) T amb = − ...
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... NXP Semiconductors 1 (Ω) 0.8 0.6 0.4 0 125 °C. (1) T amb = 85 °C. (2) T amb = 25 °C. (3) T amb = −40 °C. (4) T amb Fig 13. ON resistance as a function of input voltage 3 12. Dynamic characteristics Table 9. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see ...
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... NXP Semiconductors 12.1 Waveform and test circuits E input output LOW to OFF OFF to LOW Measurement points are given in Logic level the typical output voltage that occurs with the output load. OH Fig 15. Enable and disable times Table 10. Measurement points Supply voltage 4.3 V ...
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... NXP Semiconductors 12.2 Additional dynamic characteristics Table 12. Additional dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); V ≤ specified 2.5 ns Symbol Parameter THD total harmonic distortion −3 dB frequency f (−3dB) response α isolation (OFF-state) iso V crosstalk voltage ct Q charge injection ...
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... NXP Semiconductors Adjust f voltage to obtain 0 dBm level at output. Increase f i Fig 18. Test circuit for measuring the frequency response when channel is in ON-state Adjust f voltage to obtain 0 dBm level at input. i Fig 19. Test circuit for measuring isolation (OFF-state) a. Test circuit b. Input and output pulse definitions Fig 20 ...
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... NXP Semiconductors a. Test circuit b. Input and output pulse definitions = ΔV × C Definition: Q inj O L ΔV = output voltage variation generator resistance. gen V = generator voltage. gen Fig 21. Test circuit for measuring charge injection NX3L1G384 Product data sheet Low-ohmic single-pole single-throw analog switch E Y/Z ...
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... NXP Semiconductors 13. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1. DIMENSIONS (mm are the original dimensions UNIT max. 0.1 1.0 mm 1.1 0.15 0 0.8 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION IEC SOT353-1 Fig 22 ...
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... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1. 6× (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 1.5 mm 0.5 0.04 0.17 1.4 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...
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... NXP Semiconductors 14. Abbreviations Table 13. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model PDA Personal Digital Assistant TTL Transistor-Transistor Logic 15. Revision history Table 14. Revision history Document ID Release date NX3L1G384 v.4 20110107 • ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17. Contact information For more information, please visit: For sales office addresses, please send an email to: NX3L1G384 Product data sheet Low-ohmic single-pole single-throw analog switch 16 ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 Functional description . . . . . . . . . . . . . . . . . . . 3 9 Limiting values Recommended operating conditions Static characteristics 11.1 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 11 ...