SI3050-E-FT Silicon Laboratories Inc, SI3050-E-FT Datasheet - Page 27

• Manufacturer Part Number: SI3050-E-FT
• Description: IC VOICE DAA GCI/PCM/SPI 20TSSOP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3050-E-FT

• Package / Case: 20-TSSOP (0.173", 4.40mm Width)
• Includes: Line Voltage Monitor, Loop Current Monitor, Overload Detection, Parallel Handset Detection, Polarity Reversal Detection, TIP and
• Function: Data Access Arrangement (DAA)
• Interface: PCM, Serial, SPI
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 8.5mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Product: RF / Wireless
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Supply Current: 8.5 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

5.12.1. Line Voltage Measurement
The Si3050 reports line voltage with the LVS[7:0] bits
(Register 29) in both on- and off-hook states with a
resolution of 1 V per bit. The accuracy of these bits is
approximately ±10%. Bits 0 through 7 of this 8-bit
signed number indicate the value of the line voltage in
2s complement format. Bit 7 indicates the polarity of the
TIP/RING voltage.
If the INTE bit (Register 2, bit 7) and the POLM bit
(Register 3, bit 0) are set, a hardware interrupt is
generated on the AOUT/INT pin when Bit 7 of the LVS
BITS
LCS
30
25
20
15
10
5
0
(Si3019 Line Side Only)
0
3.3
6.6
9.9 13.2 16.5 19.8 23.1 26.4
Figure 19. Typical Loop Current LCS Transfer Function (ILIM = 0)
29.7
33
36.3 39.6 42.9 46.2 49.5 52.8 56.1 59.1 62.7 66
Loop Current (mA)
Rev. 1.31
register changes state. The edge-triggered interrupt is
cleared by writing 0 to the POLI bit (Register 4, bit 0).
The POLI bit is set each time bit 7 of the LVS register
changes state, and must be written to 0 to clear it. The
default state of the LVS register forces the LVS[7:0] bits
to 0 when the line voltage is 3 V or less. The LVFD bit
(Register 31, bit 0) disables this force-to-zero function
and allows the LVS register to display non-zero values
of
unpredictable values at line voltages between 0 to 2 V.
At 0 V, the LVS register displays all 0s.
3 V
69.3 72.6 75.9 79.2
and
Si3050 + Si3018/19
82.5 85.8 89.1 92.4 95.7 99 102.3
below.
This
Possible Overload
register
may
127
display
27