SI3050-E-FT Silicon Laboratories Inc, SI3050-E-FT Datasheet - Page 77

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SI3050-E-FT

Manufacturer Part Number
SI3050-E-FT
Description
IC VOICE DAA GCI/PCM/SPI 20TSSOP
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of SI3050-E-FT

Package / Case
20-TSSOP (0.173", 4.40mm Width)
Includes
Line Voltage Monitor, Loop Current Monitor, Overload Detection, Parallel Handset Detection, Polarity Reversal Detection, TIP and
Function
Data Access Arrangement (DAA)
Interface
PCM, Serial, SPI
Number Of Circuits
1
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
8.5mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Product
RF / Wireless
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Supply Current
8.5 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI3050-E-FT
Manufacturer:
Silicon Labs
Quantity:
1 794
Part Number:
SI3050-E-FTR
Manufacturer:
SILICONI/矽睿科技
Quantity:
20 000
Register 23. Ring Validation Control 2
Reset settings = 0010_1101
Bit
6:3
2:0
7
Name
Type
Bit
RCC[2:0]
RTO[3:0]
RDLY[2]
Name
RDLY[2]
R/W
D7
Ring Delay Bit 2.
This bit, in combination with the RDLY[1:0] bits (Register 22), sets the amount of time
between when a ring signal is validated and when a valid ring signal is indicated.
RDLY[2]
Ring Timeout.
These bits set when a ring signal is determined to be over after the most recent ring
threshold crossing.
RTO[3:0]
0000
0001
0010
1111
Ring Confirmation Count.
These bits set the amount of time that the ring frequency must be within the tolerances set
by the RAS[5:0] bits and the RMX[5:0] bits to be classified as a valid ring signal.
RCC[2:0]
000
001
010
011
100
101
110
111
...
...
0
0
0
1
D6
RDLY[1:0]
Ring Timeout
1920
Ring Confirmation Count Time
DO NOT USE THIS SETTING
00
128
256
10
11
01
D5
m
m
100
150
200
256
384
512
640
1024
m
s
s
s
RTO[3:0]
m
m
m
m
m
m
m
R/W
m
s
s
s
s
s
s
s
s
Rev. 1.31
Delay
256
1792
512
0
m
D4
s
m
m
m
s
s
s
Function
D3
Si3050 + Si3018/19
D2
RCC[2:0]
R/W
D1
D0
77

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