SI3050-E-FT Silicon Laboratories Inc, SI3050-E-FT Datasheet - Page 78

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SI3050-E-FT

Manufacturer Part Number
SI3050-E-FT
Description
IC VOICE DAA GCI/PCM/SPI 20TSSOP
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of SI3050-E-FT

Package / Case
20-TSSOP (0.173", 4.40mm Width)
Includes
Line Voltage Monitor, Loop Current Monitor, Overload Detection, Parallel Handset Detection, Polarity Reversal Detection, TIP and
Function
Data Access Arrangement (DAA)
Interface
PCM, Serial, SPI
Number Of Circuits
1
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
8.5mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Product
RF / Wireless
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Supply Current
8.5 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI3050-E-FT
Manufacturer:
Silicon Labs
Quantity:
1 794
Part Number:
SI3050-E-FTR
Manufacturer:
SILICONI/矽睿科技
Quantity:
20 000
Si3050 + Si3018/19
Register 24. Ring Validation Control 3
Reset settings = 0001_1001
Register 25. Resistor Calibration
Reset settings = xx0x_xxxx
78
Bit
5:0
Bit
3:0
7
6
7
6
5
4
Name
Name
Type
Type
Bit
Bit
RCAL[3:0] Always write back the value read.
Reserved
RCALM
RCALS
RCALD
Reserved
Name
RAS[5:0]
RNGV
Name
RCALS
RNGV
R/W
D7
D7
R
Resistor Auto Calibration.
0 = Resistor calibration is not in progress.
1 = Resistor calibration is in progress.
Manual Resistor Calibration.
0 = No calibration.
1 = Initiate manual resistor calibration. (After a manual calibration has been initiated, this bit
must be cleared within 1 ms.)
Resistor Calibration Disable.
0 = Internal resistor calibration enabled.
1 = Internal resistor calibration disabled.
This bit can be written to a 0 or 1.
Ring Validation Enable.
0 = Ring validation feature is disabled.
1 = Ring validation feature is enabled in both normal operating mode and low-power
mode.
This bit must always be written to 0.
Ring Assertion Time.
These bits set the minimum ring frequency for a valid ring signal. During ring qualification,
a timer is loaded with the RAS[5:0] field upon a TIP/RING event and decrements at a reg-
ular rate. If a second or subsequent TIP/RING event occurs after the timer has timed out
then the frequency of the ring is too low and the ring is invalidated. The difference between
RAS[5:0] and RMX[5:0] identifies the minimum duration between TIP/RING events to qual-
ify as a ring, in binary-coded increments of 2.0 ms (nominal). A TIP/RING event typically
occurs twice per ring tone period. At 20 Hz, TIP/RING events would occur every
1/(2 x 20 Hz) = 25 ms. To calculate the correct RAS[5:0] value for a frequency range
[f_min, f_max], the following equation should be used:
RCALM
R/W
D6
D6
RCALD
R/W
D5
D5
Rev. 1.31
RAS 5:0
D4
D4
Function
Function
------------------------------------------ -
2 f_min
D3
D3
RAS[5:0]
1
R/W
2 ms
D2
D2
RCAL[3:0]
R/W
D1
D1
D0
D0

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