SI3050-E-FT Silicon Laboratories Inc, SI3050-E-FT Datasheet - Page 82
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SI3050-E-FT
Manufacturer Part Number
SI3050-E-FT
Description
IC VOICE DAA GCI/PCM/SPI 20TSSOP
Manufacturer
Silicon Laboratories Inc
Datasheet
1.SI3050-KT.pdf
(112 pages)
Specifications of SI3050-E-FT
Package / Case
20-TSSOP (0.173", 4.40mm Width)
Includes
Line Voltage Monitor, Loop Current Monitor, Overload Detection, Parallel Handset Detection, Polarity Reversal Detection, TIP and
Function
Data Access Arrangement (DAA)
Interface
PCM, Serial, SPI
Number Of Circuits
1
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
8.5mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Product
RF / Wireless
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Supply Current
8.5 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI3050-E-FT
Manufacturer:
Silicon Labs
Quantity:
1 794
Part Number:
SI3050-E-FTR
Manufacturer:
SILICONI/矽睿科技
Quantity:
20 000
Si3050 + Si3018/19
Register 31. DAA Control 5
Reset settings = 0010_0000
82
6:5
Bit
7
4
3
2
1
0
Name
Type
Bit
Reserved Always write these bits to zero.
Reserved Always write these bits to zero.
FOH[1:0] Fast Off-Hook Selection.
Name
OHS2
FULL
LVFD
FILT
FULL
R/W
Full Scale Transmit and Receive Mode.
0 = Default.
1 = Transmit/receive full scale.
This bit changes the full scale of the ADC and DAC from 0 dBm min to +3.2 dBm into a 600
load (or 1 dBV into all reference impedances). When this bit is set, the DCV[1:0] bits
(Register 26) should be set to all 1s. The MINI[1:0] bits also should be set to all 0s. This ensures
correct operation of the full scale mode.
These bits determine the length of the off-hook counter. The default setting is 128 ms.
00 = 512 ms
01 = 128 ms
10 = 64 ms
11 = 8 ms
On-Hook Speed 2.
Filter Pole Selection.
0 = The receive path has a low –3 dBFS corner at 5 Hz.
1 = The receive path has a low –3 dBFS corner at 200 Hz.
Line Voltage Force Disable (Si3019 line-side only).
0 = Normal operation.
1 = The circuitry that forces the LVS register (Register 29) to all 0s at 3 V or less is disabled. The
LVS register may display unpredictable values at voltages between 0 to 2 V. All 0s are displayed
if the line voltage is 0 V.
This bit, in combination with the OHS bit (Register 16) and the SQ[1:0] bits on-hook speeds
specified are measured from the time the OH bit is cleared until loop current equals zero.
OHS
D7
0
0
1
OHS2
D6
0
1
X
FOH[1:0]
RW
SQ[1:0]
D5
00
00
11
Rev. 1.31
D4
0
26 ms ±10% (meets Australia spark quenching spec)
Mean On-Hook Speed
Less than 0.5 ms
3 ms ±10% (meets ETSI standard)
Function
OHS2
R/W
D3
D2
0
FILT
R/W
D1
LVFD
R/W
D0