PC28F128P33T85A NUMONYX, PC28F128P33T85A Datasheet
PC28F128P33T85A
Specifications of PC28F128P33T85A
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PC28F128P33T85A Summary of contents
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... Common Flash Interface capable Density and Packaging — 56-Lead TSOP package (64, 128, 256, 512- Mbit) — 64-Ball Numonyx™ Easy BGA package (64, 128, 256, 512-Mbit) — Numonyx™ QUAD+ SCSP (64, 128, 256, 512-Mbit) — 16-bit wide data bus Datasheet = V PP ...
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... Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. ...
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... Numonyx™ StrataFlash Embedded Memory (P33) Contents 1.0 Introduction .............................................................................................................. 6 1.1 Nomenclature ..................................................................................................... 6 1.2 Acronyms........................................................................................................... 6 1.3 Conventions ....................................................................................................... 7 2.0 Functional Overview .................................................................................................. 8 2.1 Virtual Chip Enable Description.............................................................................. 8 3.0 Package Information ............................................................................................... 10 3.1 56-Lead TSOP................................................................................................... 10 3.2 64-Ball Easy BGA Package .................................................................................. 11 3.3 QUAD+ SCSP Packages ...................................................................................... 14 4.0 Ballout and Signal Descriptions ............................................................................... 17 4 ...
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... Common Flash Interface ..........................................................................................77 13.1 Query Structure Output ......................................................................................77 13.2 CFI Query Identification String ............................................................................78 13.3 Device Geometry Definition .................................................................................80 13.4 Numonyx-Specific Extended Query Table ..............................................................81 14.0 Write State Machine.................................................................................................87 A Additional Information.............................................................................................94 B Ordering Information for Discrete Products .............................................................95 C Ordering Information for SCSP Products ..................................................................96 ...
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... Updated description of Burst Operation Document changes regarding burst operation with the TSOP package. Updated for 65nm lithography. October 2007 004 Define W602 Erase to Suspend. November 2007 05 Applied Numonyx template and datasheet organization. November 2007 314749-05 change on TSOP burst operation ccq Datasheet 5 ...
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... P33 product family is manufactured using Intel technology. The P33 product family is also planned on the Numonyx™ 65nm process lithography. 65nm AC timing changes are noted in this datasheet, and should be taken into account for all new designs 1 ...
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... Numonyx™ StrataFlash Embedded Memory (P33) 1.3 Conventions VCC : SR[4] : A[15: Bit : Byte : Word : Kbit : KByte : KWord : Mbit : MByte : MWord : K M November 2007 Order Number: 314749-05 Signal or voltage connection Signal or voltage level Hexadecimal number suffix Binary number suffix Denotes an individual register bit. ...
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... Functional Overview This section provides an overview of the features and capabilities of the Numonyx™ ® StrataFlash Embedded Memory (P33) device. The Kearny Family Flash memory provides density upgrades from 64-Mbit through 512- Mbit. This family of devices provides high performance at low voltage on a 16-bit data bus ...
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... Numonyx™ StrataFlash Embedded Memory (P33) Table 1: Flash Die Virtual Chip Enable Truth Table for 512 Mbit QUAD+ Package Die Selected Lower Param Die Upper Param Die Table 2: Flash Die Virtual Chip Enable Truth Table for 512 Mbit TSOP / Easy BGA Package ...
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... Package Height A Standoff A 1 Package Body Thickness A 2 Lead Width b Lead Thickness c Package Body Length D 1 Package Body Width E Lead Pitch e Terminal Dimension D Lead Tip Length L Datasheet 10 Numonyx™ StrataFlash See Note Detail Millimeters Min Nom Max - - 1.200 0.050 - - 0.002 0.965 0.995 1 ...
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... Numonyx™ StrataFlash Embedded Memory (P33) Table 3: TSOP Package Dimensions (Sheet Product Information Symbol Lead Count N Lead Tip Angle ý Seating Plane Coplanarity Y Lead to Package Offset Z Notes: 1. One dimple on package denotes Pin two dimples, then the larger dimple denotes Pin 1. ...
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... Daisy Chain Evaluation Unit information is at Nu;monyx™ Flash Memory Packaging Technology developer.Numonyx.com/design/flash/packtech. Figure 3: 256-Mbit and 512-Mbit Easy BGA Mechanical Specifications Ball A1 Corner Top View - Ball side down A1 A2 Datasheet 12 Numonyx™ StrataFlash Millimeters Symbol Min Nom b 0.330 0.430 0.530 D 9.900 10.000 10.100 E 7.900 8.000 8.100 [e] - 1.000 ...
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... Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along D Corner to Ball A1 Distance Along E Notes: 1. Daisy Chain Evaluation Unit information is at Numonyx™ Flash Memory Packaging Technology developer.numonyx.com/design/flash/packtech. November 2007 Order Number: 314749-05 Millimeters Symbol Min Nom ...
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... Top View - Ball Down A 2 Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along E Corner to Ball A1 Distance Along D Datasheet 14 Numonyx™ StrataFlash ...
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... Numonyx™ StrataFlash Embedded Memory (P33) Figure 5: 256-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x11x1.0 mm Index Mark Top View - Ball Down A2 Note: Dimensions A1, A2, and b are preliminary Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length ...
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... L M Top View - Ball Down A2 Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along E Corner to Ball A1 Distance Along D Datasheet 16 Numonyx™ StrataFlash ...
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... Numonyx™ StrataFlash Embedded Memory (P33) 4.0 Ballout and Signal Descriptions 4.1 Signal Ballout Figure 7: 56-Lead TSOP Pinout (64/128/256/512-Mbit) 1 A16 A15 2 3 A14 4 A13 5 A12 6 A11 7 A10 A23 10 A22 11 A21 12 VSS 13 VCC 14 WE# 15 WP# 16 A20 17 A19 18 A18 A24 27 A25 28 VSS Notes: 1 ...
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... Top View- Ball side down Notes the least significant address bit. 2. A23 is valid for 128-Mbit densities and above; otherwise connect. 3. A24 is valid for 256-Mbit densities and above; otherwise connect. 4. A25 is valid for 512-Mbit densities; otherwise connect. Datasheet 18 Numonyx™ StrataFlash A13 VCC A18 A22 ...
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... A23 is valid for 256-Mbit densities and above; otherwise connect. 3. A24 is valid for 512-Mbit densities and above; otherwise connect. 4. F2-CE# and F2-OE# are no connects. 4.2 Signal Descriptions This section has signal descriptions for the various Numonyx™ StrataFlash Memory (P33) device packages. November 2007 Order Number: 314749- ...
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... Output Power Supply: Output-driver source voltage. VSS Power Ground: Connect to system ground. Do not float any VSS connection. Reserved for Future Use: Reserved by Numonyx for future device functionality and enhancement. RFU — These should be treated in the same way as a Don’t Use (DU) signal. ...
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... Output Power Supply: Output-driver source voltage. VSS Power Ground: Connect to system ground. Do not float any VSS connection. Reserved for Future Use: Reserved by Numonyx for future device functionality and enhancement. RFU — These should be treated in the same way as a Don’t Use (DU) signal. ...
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... Datasheet 22 Numonyx™ StrataFlash Top Param Die (256-Mbit) Bottom Param Die (256-Mbit) Top Param Die (256-Mbit) Bottom Param Die (256-Mbit) max Table 10 show the Numonyx™ StrataFlash ® Embedded Memory (P33) RST# VCC VPP VCCQ VSS DQ[15:0] WAIT RST# VCC VPP ...
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... Numonyx™ StrataFlash Embedded Memory (P33) Table 8: Discrete Top Parameter Memory Maps (all packages) Size Blk (KB 3FC000 - 3FFFFF 32 63 3F0000 - 3F3FFF 128 62 3E0000 - 3EFFFF 128 56 380000 - 38FFFF 128 55 370000 - 37FFFF 128 54 360000 - 36FFFF 128 1 010000 - 01FFFF 128 0 000000 - 00FFFF Size ...
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... The Dual-Die memory map are the same for both parameter options. Table 10: 512-Mbit Top and Bottom Parameter Memory Map (Easy BGA, TSOP, and QUAD+ SCSP) (Sheet Die Stack Config 256-Mbit Top Parameter Die Datasheet 24 Numonyx™ StrataFlash 64-Mbit 256-Mbit 512-Mbit Flash (2x256-Mbit w/ 1CE) Size Blk (KB) 32 ...
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... Numonyx™ StrataFlash Embedded Memory (P33) Table 10: 512-Mbit Top and Bottom Parameter Memory Map (Easy BGA, TSOP, and QUAD+ SCSP) (Sheet Die Stack Config 256-Mbit Bottom Parameter Die Note: Refer to the appropriate 256-Mbit Memory Map ( is referenced in K-Bytes where a byte=8 bits. Block Address range is referenced in K-Words where a Word is the size of the flash output bus (16 bits) ...
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... In typical operation VPP program voltage 40Mhz burst operation on the TSOP package has a max V regarding synchronous burst operation with the TSOP package. Datasheet 26 Numonyx™ StrataFlash . Minimum DC voltage is –0 input/output signals and –0 0.5 V, which, during transitions, may overshoot to CCQ CCQ ...
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... Numonyx™ StrataFlash Embedded Memory (P33) 6.0 Electrical Specifications 6.1 DC Current Characteristics Table 13: DC Current Characteristics (Sheet Sym Parameter I Input Load Current LI Output I Leakage DQ[15:0], LO WAIT Current 64-Mbit 128-Mbit Standby, CCS CC 256-Mbit I Power Down CCD 512-Mbit Asynchronous Single- Word MHz (1 CLK) ...
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... LKOQ CCQ Notes: 1. Synchronous read mode is not supported with TTL inputs can undershoot to –0.4 V and ≤ V inhibits erase and program operations. Do not use V PP PPLK Datasheet 28 Numonyx™ StrataFlash CMOS TTL Inputs Inputs (V = CCQ (V = CCQ 2 3 Typ Max Typ Max ...
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... Numonyx™ StrataFlash Embedded Memory (P33) 7.0 AC Characteristics 7.1 AC Test Conditions Figure 12: AC Input/Output Reference Waveform V CCQ Input V /2 CCQ 0V Note: AC test inputs are driven at V CCQ and fall times (10% to 90%) < 5 ns. Worst-case speed occurs at V Figure 13: Transient Equivalent Testing Load Circuit Notes: 1 ...
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... CE# high to WAIT high-Z EHTZ R15 t OE# low to WAIT valid GLTV R16 t OE# low to WAIT in low-Z GLTX R17 t OE# high to WAIT in high-Z GHTZ Latching Specifications Datasheet 30 Numonyx™ StrataFlash Signals Min Typ Max RST#, CLK, ADV#, WP# Data, WAIT Parameter 256/512M TSOP 256/512M ...
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... Numonyx™ StrataFlash Embedded Memory (P33) Table 17: AC Read Specifications - 130nm (Sheet Num Symbol R101 t Address setup to ADV# high AVVH R102 t CE# low to ADV# high ELVH R103 t ADV# low to output valid VLQV R104 t ADV# pulse width low VLVH R105 t ADV# pulse width high ...
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... This is the recommended specification for all new designs supporting both 130nm and 65nm lithos, or for new designs that will use the 65nm lithography. All other timings not listed here remain the same as referenced by “AC Read Specifications - 130nm” Datasheet 32 Numonyx™ StrataFlash Parameter – t after CE#’s falling edge without impact to t ELQV ...
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... Numonyx™ StrataFlash Embedded Memory (P33) Figure 15: Asynchronous Single-Word Read (ADV# Low) Address [A] ADV# CE# [E} OE# [G] R15 WAIT [ Data [D/Q] RST# [P] Note: WAIT shown deasserted during asynchronous read mode (RCR 10=0, WAIT asserted low). Figure 16: Asynchronous Single-Word Read (ADV# Latch) ...
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... WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either during or one data cycle before valid data. 2. This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by CE# deassertion after the first word in the burst. Datasheet 34 Numonyx™ StrataFlash R1 R1 R106 R108 R306 R2 ...
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... Numonyx™ StrataFlash Embedded Memory (P33) Figure 19: Continuous Burst Read, showing an Output Delay Timing R301 R302 R306 CLK [C] R2 R101 Address [A] R106 R105 R105 ADV# [V] R303 R102 R3 CE# [E] OE# [G] R15 WAIT [T] Data [D/Q] Notes: 1. WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either during or one data cycle before valid data ...
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... Add the write operations results in a RCR or block lock status change, for the subsequent read operation to reflect this change. 11. These specs are required only when the device synchronous mode and clock is active during address setup phase. Datasheet 36 Numonyx™ StrataFlash Parameter ) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high ELEH = ...
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... Numonyx™ StrataFlash Embedded Memory (P33) Figure 21: Write-to-Write Timing W5 Address [A] W2 CE# [E} WE# [W] OE# [G] Data [D/Q] W1 RST# [P] Figure 22: Asynchronous Read-to-Write Timing R2 Address [A] R3 CE# [E} OE# [G] WE# [W] WAIT [ Data [D/Q] R5 RST# [P] Note: WAIT deasserted during asynchronous read and during write. WAIT High-Z during write per OE# deasserted. ...
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... R102 ADV R303 R3 CE# [E] OE# [G] WE# WAIT [T] Dat a [D/Q] Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR 10=0, WAIT asserted low). Clock is ignored during write operation. Datasheet 38 Numonyx™ StrataFlash W18 W14 Latency Count R11 R11 R13 ...
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... Numonyx™ StrataFlash Embedded Memory (P33) Figure 25: Write-to-Synchronous Read Timing CLK W5 Address [A] ADV# W2 CE# [ WE# [W] OE# [G] WAIT [T] W4 Data [D/Q] W1 RST# [P] Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR 10=0, WAIT asserted low). 7.5 Program and Erase Characteristics ...
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... Averaged over entire device. 3. W602 is the typical time between an initial block erase or erase resume command and the a subsequent erase suspend command. Violating the specification repeatedly during any particular block erase may cause erase failures. Datasheet 40 Numonyx™ StrataFlash V PPL Min Typ - ...
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... Numonyx™ StrataFlash Embedded Memory (P33) 8.0 Power and Reset Specifications 8.1 Power-Up and Power-Down Power supply sequencing is not required if VPP is connected to VCC or VCCQ. Otherwise V and V should attain their minimum operating voltage before applying V CC CCQ Power supply transitions should only occur when RST# is low. This protects the device from accidental programming or erasure during power transitions ...
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... Two-line control and correct de-coupling capacitor selection suppress transient voltage peaks. Because Numonyx MLC flash memory devices draw their power from VCC, VPP, and VCCQ, each power connection should have a 0.1 µF ceramic capacitor to ground. High- frequency, inherently low-inductance capacitors should be placed as close as possible to package leads ...
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... ADV# edge or the next valid CLK edge with ADV# low (WE# and RST# must be V Bus cycles to/from the Numonyx™ StrataFlash conform to standard microprocessor bus operations. operations and the logic levels that must be applied to the device control signal inputs. ...
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... CPU initialization may occur because the flash memory may be providing status information rather than array data. Flash memory devices from Numonyx allow proper CPU initialization following a system reset through the use of the RST# input. RST# should be controlled by the same low-true reset signal that resets the system CPU ...
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... Numonyx™ StrataFlash Embedded Memory (P33) Table 23: Command Bus Cycles Mode Command Read Array Read Device Identifier Read CFI Query Read Status Register Clear Status Register Word Program (3) Program Buffered Program Buffered Enhanced Factory (4) Program (BEFP) Erase Block Erase Program/Erase Suspend ...
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... Suspend 0xD0 Suspend Resume Datasheet 46 Numonyx™ StrataFlash Description Places the device in Read Array mode. Array data is output on DQ[15:0]. Places the device in Read Status Register mode. The device enters this mode after a program or erase command is issued. SR data is output on DQ[7:0]. Places device in Read Device Identifier mode. Subsequent reads output manufacturer/device codes, Configuration Register data, Block Lock status, or Protection Register data on DQ[15:0] ...
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... Numonyx™ StrataFlash Embedded Memory (P33) Table 24: Command Codes and Definitions (Sheet Mode Code Device Mode 0x60 Lock Block Setup 0x01 Lock Block Block Locking/ Unlocking 0xD0 Unlock Block 0x2F Lock-Down Block Program Protection Protection 0xC0 Register Setup Read Configuration ...
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... Device Write Status (DWS) 6 Erase Suspend Status (ESS) 5 Erase Status (ES) 4 Program Status (PS Status (VPPS) PP Datasheet 48 Numonyx™ StrataFlash Program V Status PP Status ES PS VPPS Device is busy; program or erase cycle in progress; SR[0] valid Device is ready; SR[6:1] are valid Erase suspend not in effect. ...
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... Numonyx™ StrataFlash Embedded Memory (P33) Table 25: Status Register Description (Sheet Status Register (SR) 2 Program Suspend Status (PSS) 1 Block-Locked Status (BLS) 0 BEFP Write Status (BWS) Note: Always clear the Status Register prior to resuming erase operations. It avoids Status Register ambiguity when issuing commands during Erase Suspend command sequence error occurs during an erase-suspend state, the Status Register contains the command sequence error status (SR[7,5,4] set) ...
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... Considerations” on page 55 Refer to Table 27, “LC and Frequency Support” on page 51 Datasheet 50 Numonyx™ StrataFlash 0 =WAIT signal is active low 1 =WAIT signal is active high (default) 0 =Data held for a 1-clock data cycle 1 =Data held for a 2-clock data cycle (default) 0 =WAIT deasserted with valid data ...
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... Numonyx™ StrataFlash Embedded Memory (P33) Figure 27: First-Access Latency Count CLK [C] Valid Address [A] Address ADV# [V] Code 0 (Reserved) DQ [D/Q] Output 15-0 Code 1 (Reserved DQ [D/Q] 15-0 Code 2 DQ [D/Q] 15-0 Code 3 DQ [D/Q] 15-0 Code 4 DQ [D/Q] 15-0 Code 5 DQ [D/Q] 15-0 ...
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... Table 28: WAIT Functionality Table (Sheet Condition CE# = ‘1’, OE# = ‘X’ or CE# = ‘0’, OE# = ‘1’ CE# =’0’, OE# = ‘0’ Synchronous Array Reads Synchronous Non-Array Reads Datasheet 52 Numonyx™ StrataFlash 0 1 Address Code 3 High-Z R103 Figure 16, “Asynchronous Single-Word Read (ADV# Latch)” on ...
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... Numonyx™ StrataFlash Embedded Memory (P33) Table 28: WAIT Functionality Table (Sheet Condition All Asynchronous Reads All Writes Notes: 1. Active: WAIT is asserted until data becomes valid, then deasserts. 2. When OE during writes, WAIT = High-Z. IH 11.1.0.6 Data Hold For burst read operations, the Data Hold (DH) bit determines whether the data output remains valid on DQ[15:0] for one or two clock cycles. This period of time is called the “ ...
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... When BW is set, burst wrapping does not occur (default). When BW is cleared, burst wrapping occurs. Datasheet 54 Numonyx™ StrataFlash Table 29 shows the synchronous burst sequence for all burst Burst Addressing Sequence (DEC) 8-Word Burst ...
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... Numonyx™ StrataFlash Embedded Memory (P33) 11.1.0.11 Burst Length The Burst Length bits (BL[2:0]) selects the linear burst length for all synchronous burst reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, and continuous word. Continuous burst accesses are linear only, and do not wrap within any word length ...
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... Block Is not Locked-Down • Block Is Locked-Down Read Configuration Register Lock Register 0 Datasheet 56 Numonyx™ StrataFlash delay. (see Section 7.0, “AC Characteristics” on page 50). Subsequent data is output on valid CLK edges Section 9.6, “Device Command Bus Cycles” on page 44 Table 30, “Device Identifier Information” ...
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... Each Programming Region should contain only code or data but not both. The following terms define the difference between code and data. System designs must use these definitions when partitioning their code and data for the Numonyx™ ® ...
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... When the Buffered Programming Setup command is issued (see Command Bus Cycles” on page the availability of the buffer. SR[7] indicates buffer availability: if set, the buffer is Datasheet 58 Numonyx™ StrataFlash min/max values. PPL was outside of its acceptable limits. If SR[1] is set, PP Section 5.2, “Operating Conditions” on page ...
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... Numonyx™ StrataFlash Embedded Memory (P33) available; if cleared, the buffer is not available. To retry, issue the Buffered Programming Setup command again, and re-check SR[7]. When SR[7] is set, the buffer is ready for loading. (see On the next write, a word count is written to the device at the buffer address. This tells the device how many data words will be written to the buffer the maximum size of the buffer ...
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... Two basic sequences repeat in this phase: loading of the write buffer, followed by buffer data programming to the array. For BEFP, the count value for buffer loading is always the maximum buffer size of 32 words. During the buffer-loading sequence, data is Datasheet 60 Numonyx™ StrataFlash = 25 °C ± 5 °C C PPH level, etc.). If an error is detected, PP ® ...
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... Numonyx™ StrataFlash Embedded Memory (P33) stored to sequential buffer locations starting at address 0x00. Programming of the buffer contents to the flash memory array starts as soon as the buffer is full. If the number of words is less than 32, the remaining buffer locations must be filled with 0xFFFF. Caution: The buffer must be completely filled for programming to occur ...
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... V be above V and the block must be unlocked (see PPLK on page 73). Datasheet 62 Numonyx™ StrataFlash must remain at its programming level, and WP# must remain PP 70). , programming operations halt and SR[3] is set indicating a V PPLK is less than V PP ...
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... Numonyx™ StrataFlash Embedded Memory (P33) During a block erase, the WSM executes a sequence of internally-timed events that conditions, erases, and verifies all bits within the block. Erasing the flash memory array changes “zeros” to “ones”. Memory array bits that are ones can be changed to zeros only by programming the block ...
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... Section 11.4.4, “Erase Protection” on page The Numonyx™ StrataFlash defined areas in the main array that can be configured as One-Time Programmable (OTP) for the highest level of security. These include the four 32 KB parameter blocks together as one and the three adjacent 128 KB main blocks. This is available for top or bottom parameter devices ...
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... Numonyx™ StrataFlash Embedded Memory (P33) 11.4.6.4 Block Lock Status The Read Device Identifier command is used to determine a block’s lock status (see Section 11.2.3, “Read Device Identifier” on page addressed block’s lock status; DQ0 is the addressed block’s lock bit, while DQ1 is the addressed block’ ...
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... This option allows all main blocks (plus the four 32-KB parameter blocks together as one block configured as OTP to prevent further program and erase operations. This option is available for top or bottom parameter devices. Ask your local Numonyx representative for details about either of these Selectable OTP implementations. 11.4.8 ...
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... Embedded Memory (P33) The first 128-bit Protection Register is comprised of two 64-bit (8-word) segments. The lower 64-bit segment is pre-programmed at the Numonyx factory with a unique 64-bit number. The other 64-bit segment, as well as the other sixteen 128-bit Protection Registers, are blank. Users can program these registers as needed. When programmed, ...
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... Protection Registers. Programming a bit in Lock Register 1 locks the corresponding 128-bit Protection Register. Caution: After being locked, the Protection Registers cannot be unlocked. Datasheet 68 Numonyx™ StrataFlash Table 30, “Device Identifier Information” on page 56 67). Figure 40, “Protection Register Programming Flowchart” on Section 9.6, “Device Command Bus Cycles” on page 56). ...
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... Numonyx™ StrataFlash Embedded Memory (P33) 12.0 Flowcharts Figure 33: Word Program Flowchart Start Write 0x40, (Setup) Word Address Write Data, (Confirm) Word Address Read Status Register 0 SR[7] = Suspend? 1 Full Status Check (if desired) Program Complete Read Status Register V Range 1 PP SR[3] = ...
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... Read Array Data Done No Reading Yes Program Resume Read Array Write D0h Any Address Program Read Array Resumed Datasheet 70 Numonyx™ StrataFlash PROGRAM SUSPEND / RESUME PROCEDURE Bus Command Operation Read Write Status Program Write Suspend Read Standby Standby Program Read Write ...
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... Numonyx™ StrataFlash Embedded Memory (P33) Figure 35: Buffer Program Flowchart Start Device Use Single Word Supports Buffer No Writes? Yes Set Timeout or Loop Counter Get Next Target Address Issue Write to Buffer Command E8h and Block Address Read Status Register (at Block Address) Is WSM Ready? SR ...
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... First-word address to be programmed within the target block must be aligned on a write -buffer boundary rite-buffer contents are programmed sequentially to the flash array starting at the first word address (W SM internally increments addressing ). Datasheet 72 Numonyx™ StrataFlash Program & Verify Phase Read Status Reg. ...
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... Numonyx™ StrataFlash Embedded Memory (P33) Figure 37: Block Erase Flowchart Start Write 0x20, (Block Erase) Block Address Write 0xD0, (Erase Confirm) Block Address Read Status Register Suspend 0 SR[7] = Erase 1 Full Erase Status Check (if desired) Block Erase Complete FULL ERASE STATUS CHECK PROCEDURE ...
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... Program ? Read Array No Data Done? Yes Erase Resume Write D0h Any Address Erase Resumed Read Status Write 70h Any Address Datasheet 74 Numonyx™ StrataFlash ERASE SUSPEND / RESUME PROCEDURE Bus Command Operation Read Write Status Erase Write Suspend Read Standby 0 Standby Erase 0 ...
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... Numonyx™ StrataFlash Embedded Memory (P33) Figure 39: Block Lock Operations Flowchart Start Lock Setup Write 60h Block Address Lock Confirm Write 01 ,D0,2Fh Block Address Read ID Plane Write 90h Read Block Lock Status Locking No Change ? Yes Read Array Write FFh Any Address ...
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... Range Error SR[4] = Program Error 0 Register Locked; 1 SR[1] = Program Aborted 0 Program Successful Datasheet 76 Numonyx™ StrataFlash Bus Command Operation Program Write PR Setup Protection Write Program Read None Idle None Program Protection Register operation addresses must be within the Protection Register address space. Addresses outside this space will return an error ...
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... Numonyx™ StrataFlash Embedded Memory (P33) 13.0 Common Flash Interface The Common Flash Interface (CFI) is part of an overall specification for multiple command-set and control-interface descriptions. This appendix describes the database structure containing the data returned by a read operation after issuing the CFI Query command (see Section 9.6, “ ...
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... BA = Block Address beginning location (i.e., 08000h is block 1’s beginning location when the block size is 32-KWord). 3. Offset 15 defines “P” which points to the Primary Numonyx-specific Extended Query Table. 13.2 CFI Query Identification String The Identification String provides verification that the component supports the Common Flash Interface specification ...
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... Numonyx™ StrataFlash Embedded Memory (P33) Table 37: System Interface Information Offset Length 1Bh 1 V logic supply minimum program/erase voltage CC bits 0–3 BCD 100 mV bits 4–7 BCD volts 1Ch 1 V logic supply maximum program/erase voltage CC bits 0–3 BCD 100 mV bits 4–7 BCD volts ...
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... Datasheet 80 Numonyx™ StrataFlash Description n “n” such that device size = 2 in number of bytes Flash device interface code assignment: "n" such that n+1 specifies the bit field that represents the flash device width capabilities as described in the table ...
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... Numonyx™ StrataFlash Embedded Memory (P33) 13.4 Numonyx-Specific Extended Query Table Table 39: Primary Vendor-Specific Extended Query (1) Length Offset P = 10Ah (P+0)h 3 Primary extended query table (P+1)h Unique ASCII string “PRI“ (P+2)h (P+3)h 1 Major version number, ASCII (P+4)h 1 Minor version number, ASCII ...
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... Datasheet 82 Numonyx™ StrataFlash Description (Optional flash features and commands) Number of Protection register fields in JEDEC ID space. “00h,” indicates that 256 protection fields are available Protection Field 1: Protection Description This field describes user-available One Time Programmable (OTP) Protection register bytes. Some are pre-programmed with device-unique serial numbers. Others are user programmable. Bits 0– ...
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... Numonyx™ StrataFlash Embedded Memory (P33) Table 42: Partition and Erase Block Region Information (1) Offset P = 10Ah Bottom Top Number of device hardware-partition regions within the device single hardware partition device (no fields follow). x specifies the number of device partition regions containing (P+23)h (P+23)h one or more contiguous erase block regions. ...
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... Control Mode invalid size in bytes (P+47)h (P+47)h bits 40-46 = Reserved; bit 47 = Legacy flash operation (ignore 23:16 & 39:32) Datasheet 84 Numonyx™ StrataFlash Description (Optional flash features and commands) ® Embedded Memory (P33) See table below Address Len Bot ...
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... Numonyx™ StrataFlash Embedded Memory (P33) Table 45: Partition and Erase Block Region Information Address 64-Mbit –B 12D: --01 12E: --24 12F: --00 130: --01 131: --00 132: --11 133: --00 134: --00 135: --02 136: --03 137: --00 138: --80 139: --00 13A: --64 --00 13B: 13C: --02 13D: --03 13E: --00 13F: --80 140: --00 141: --00 142: --00 143: ...
Page 86
... Datasheet 86 Numonyx™ StrataFlash Description (Optional flash features and commands) 512-Mbit –B –T die 2 (T) die 1 (T) die 2 (B) --FF --10 --FF --FF --20 --FF --FF --00 --FF --FF --00 --FF --FF --10 --FF ® ...
Page 87
... Numonyx™ StrataFlash Embedded Memory (P33) 14.0 Write State Machine Figure 41 through based on incoming commands. Only one partition can be actively programming or erasing at a time. Each partition stays in its last read state (Read Array, Read Device ID, CFI Query or Read Status Register) until a new command changes it. The next WSM state does not depend on the partition’ ...
Page 88
... Factory Program BEFP Mode BEFP Program and Verify Busy (if Block Address given matches address given on BEFP Setup command). Commands treated as data. (7) Busy Datasheet 88 Numonyx™ StrataFlash Command Input to Chip and resulting Chip Next State BE Confirm, Buffered P/E Buffered BP / Prg / Erase Enhanced ...
Page 89
... Numonyx™ StrataFlash Embedded Memory (P33) Figure 43: Write State Machine—Next State Table (Sheet OTP Current Chip Setup (7) State (C0H) OTP Ready Setup Ready Lock/CR Setup (Lock Error) Setup OTP Busy Setup Busy Word Program Suspend Setup BP Load 1 BP Confirm if Data load into Program Buffer is ...
Page 90
... Program BEFP Program and Verify Busy (if Block Address BEFP Mode given matches address given on BEFP Setup Busy command). Commands treated as data. (7) Datasheet 90 Numonyx™ StrataFlash Command Input to Chip and resulting Chip Next State Lock Lock-Down Write RCR Block Address Block Block (4) ...
Page 91
... Numonyx™ StrataFlash Embedded Memory (P33) Figure 45: Write State Machine—Next State Table (Sheet Output Next State Table Word Read Program (2) Array Current chip state Setup (3,4) (FFH) (10H/40H) BEFP Setup, BEFP Pgm & Verify Busy, Erase Setup, OTP Setup, ...
Page 92
... Busy, Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, BEFP modes). 6. BEFP writes are only allowed when the status register bit # else the data is ignored. Datasheet 92 Numonyx™ StrataFlash Command Input to Chip and resulting Output Mux Next State Lock Lock-Down Write CR ...
Page 93
... Numonyx™ StrataFlash Embedded Memory (P33) 7. The "current state" is that of the "chip" and not of the "partition"; Each partition "remembers" which output (Array, ID/CFI or Status) it was last pointed to on the last instruction to the "chip", but the next state of the chip does not depend on where the partition's output multiplexer (mux) is presently pointing to ...
Page 94
... Migration Guide for Spansion* S29GLxxxN to Numonyx™ StrataFlash 306668 Application Note 813 Notes: 1. Please call the Numonyx Literature Center at (800) 548-4725 to request Numonyx documentation. International customers should contact their local Numonyx or distribution sales office. 2. Visit Numonyx’s World Wide Web home page at 3. ...
Page 95
... Numonyx™ StrataFlash Embedded Memory (P33) Appendix B Ordering Information for Discrete Products Figure 47: Decoder Package Designator TE = 56- Lead TSOP, leaded JS = 56- Lead TSOP, lead- free RC = 64- Ball Easy BGA , leaded PC = 64- Ball Easy BGA , lead- free Product Line Designator Intel® Flash Memory ...
Page 96
... The “B” parameter shown in the table and chart above is used for both “top” and “bottom” options in 512-Mbit densities. The “T” (Top Boot) configuration is no longer available as it was identical to the Bottom Boot configuration in this density. Datasheet 96 Numonyx™ StrataFlash ...