CY7C1520KV18-200BZC Cypress Semiconductor Corp, CY7C1520KV18-200BZC Datasheet - Page 10

• Manufacturer Part Number: CY7C1520KV18-200BZC
• Description: IC SRAM 72MBIT 200MHZ 165-FPBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1520KV18-200BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 72M (2M x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and V
driver impedance. The value of RQ must be 5x the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175Ω and 350Ω
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the DDR II to simplify data capture
on high speed systems. Two echo clocks are generated by the
DDR II. CQ is referenced with respect to C and CQ is referenced
with respect to C. These are free running clocks and are synchro-
nized to the output clock of the DDR II. In single clock mode, CQ
is generated with respect to K and CQ is generated with respect
to K. The timing for the echo clocks is shown in the
Characteristics
Application Example
Figure 1
Document Number: 001-00437 Rev. *J
Echo Clock1/Echo Clock#1
Echo Clock2/Echo Clock#2
MASTER
ASIC)
(CPU
BUS
or
shows two DDR II used in an application.
Source CLK#
Return CLK#
on page 25.
Cycle Start#
Return CLK
Source CLK
Addresses
SS
R/W#
DQ
to allow the SRAM to adjust its output
R = 50ohms
DQ
Vterm = 0.75V
Vterm = 0.75V
,
with V
A
LD#
DDQ
SRAM#1
R/W#
Figure 1. Application Example
= 1.5 V. The
C C#
Switching
CQ/CQ#
K
K#
ZQ
R = 250ohms
PLL
These chips use a PLL that is designed to function between
120 MHz and the specified maximum clock frequency. During
power up, when the DOFF is tied HIGH, the PLL is locked after
20 μs of stable clock. The PLL can also be reset by slowing or
stopping the input clock K and K for a minimum of 30 ns.
However, it is not necessary to reset the PLL to lock to the
desired frequency. The PLL automatically locks 20 μs after a
stable clock is presented. The PLL may be disabled by applying
ground to the DOFF pin. When the PLL is turned off, the device
behaves in DDR-I mode (with one cycle latency and a longer
access time).
CY7C1516KV18, CY7C1527KV18
CY7C1518KV18, CY7C1520KV18
DQ
A
LD#
SRAM#2
R/W#
C C#
CQ/CQ#
K
K#
ZQ
R = 250ohms
Page 10 of 33
[+] Feedback