SPIO-4/NOPB National Semiconductor, SPIO-4/NOPB Datasheet - Page 20

• Manufacturer Part Number: SPIO-4/NOPB
• Description: BOARD INTERFACE FOR AFE
• Manufacturer: National Semiconductor

Specifications of SPIO-4/NOPB

• Main Purpose: Interface, Analog Front End (AFE)
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: SAM3U, XC6SLX16
• Primary Attributes: USB Powered or External Supply
• Secondary Attributes: GUI, I2C, SPI, USB Interfaces
• Accessory Type: Digital Interface Board
• Msl: MSL 1 - Unlimited
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SPI0-4/NOPB; SPI0-4/NOPB

D
C
B
A
3,4
3,4
A[23:1]
D[15:0]
3
3
3
3
3
SCC_TD
SCC_TF
NCS3
PCK
SCC_CLK
D11
D12
D13
D14
D15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A1
A2
A3
A4
A5
A6
A7
A8
A9
5
5
RSTUFF OPTIONS TO SUPPORT
SERIAL AND PARALLEL FPGA CONFIG
D7
0R R74
0R
DNS R73
DNS
0R R76
0R
DNS R75
DNS
0R R78
0R
DNS R77
DNS
3
3,4
3,4
3,4
3,4
3,4
3,4
3
3
3
2
3
R74
R76
R78
FPGA_INIT_N
R73
R75
R77
CLK_12MHZ
FPGA_M0
NCS2
FPGA_M1
PCK1
NWAIT
NCS0
DATA_D7_CFG_D0
DATA_D7_CFG_D0
NWE
NRD
NBS0
NBS1
FPGA_CCLK
FPGA_CFG_CSN
CCLK R15
NWAIT
NOTE:D0-7 SWAPPED GOING INTO CONFIG BITS
NCS0
NRD
NBS0
NBS1
FPGA_CFG_CSN
DATA_D7_CFG_D0
FPGA_CCLK
D2
D4
D15
D14
D13
D12
D11
D10
D9
D8
D5
D6
D3
D1
D0
4
4
V10
U10
U11
V13
U13
V14
V16
U16
V11
R15
R13
N12
P12
R11
R10
T10
T11
T13
T14
T15
R3
U3
U5
U7
U8
R8
R7
R5
N5
T4
T5
V7
T7
V8
T8
V6
V3
V4
V5
V9
T6
T3
T9
P6
IO_L62P_D5_2
IO_L65P_INIT_B_2
IO_L63P_2
IO_L49P_D3_2
IO_L48N_RDWR_B_VREF_2
IO_L43N_2
IO_L43P_2
IO_L46N_2
IO_L41N_VREF_2
IO_L41P_2
IO_L31N_GCLK30_D15_2
IO_L30N_GCLK0_USERCCLK_2
IO_L30P_GCLK1_D13_2
IO_L29N_GCLK2_2
IO_L23P_2
IO_L16N_VREF_2
IO_L14N_D12_2
IO_L14P_D11_2
IO_L3N_MOSI_CSI_B_MISO0_2
IO_L12N_D2_MISO3_2
IO_L12P_D1_MISO2_2
IO_L1N_M0_CMPMISO_2
IO_L2N_CMPMOSI_2
IO_L2P_CMPCLK_2
IO_L45N_2
IO_L65N_CSO_B_2
IO_L63N_2
IO_L49N_D4_2
IO_L32N_GCLK28_2
IO_L45P_2
IO_L23N_2
IO_L62N_D6_2
IO_L1P_CCLK_2
IO_L3P_D0_DIN_MISO_MISO1_2
IO_L13P_M1_2
IO_L13N_D10_2
IO_L16P_2
IO_L29P_GCLK3_2
IO_L31P_GCLK31_D14_2
IO_L32P_GCLK29_2
IO_L46P_2
IO_L48P_D7_2
IO_L64P_D8_2
IO_L64N_D9_2
U5-3
U5-3
REQUIRED SIGNALS TO CONFIG FPGA
VIA SERIAL OR BYTE WIDE (SELECTMAP)
XC6SLX9CSG324
XC6SLX9CSG324
D7 R5
D6 T3
D5 R3
D4 V5
D3 U5
D2 V14
D1 T14
DO_DIN R13
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
CSI_B T13
RDWR_B T5
INIT U3
M1 N12
M0 T15
P9
R12
R6
U14
U4
U9
3p3V
3
3
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
H14
C17
C18
D17
D18
G18
G16
H18
H17
H16
H15
U17
N18
N17
N16
M18
M16
N15
N14
U18
G14
H12
G13
H13
M14
M13
J18
K18
K17
K16
J16
L15
K15
E16
E18
F18
F17
F16
F15
P18
P17
T17
P15
P16
L18
L17
L16
T18
F14
K12
K13
J13
K14
L12
L13
L14
IO_L44N_A2_M1DQ7_1
IO_L45N_A0_M1LDQSN_1
IO_L45P_A1_M1LDQS_1
IO_L41N_GCLK8_M1CASN_1
IO_L44P_A3_M1DQ6_1
IO_L42P_GCLK7_M1UDM_1
IO_L41P_GCLK9_IRDY1_M1RASN_1
IO_L36N_A8_M1BA1_1
IO_L29P_A23_M1A13_1
IO_L29N_A22_M1A14_1
IO_L31P_A19_M1CKE_1
IO_L31N_A18_M1A12_1
IO_L33P_A15_M1A10_1
IO_L33N_A14_M1A4_1
IO_L35N_A10_M1A2_1
IO_L35P_A11_M1A7_1
IO_L1N_A24_VREF_1
IO_L1P_A25_1
IO_L38N_A4_M1CLKN_1
IO_L38P_A5_M1CLK_1
IO_L43N_GCLK4_M1DQ5_1
IO_L43P_GCLK5_M1DQ4_1
IO_L37N_A6_M1A1_1
IO_L37P_A7_M1A0_1
IO_L49N_M1DQ11_1
IO_L49P_M1DQ10_1
IO_L51P_M1DQ12_1
IO_L52P_M1DQ14_1
IO_L48N_M1DQ9_1
IO_L48P_HDC_M1DQ8_1
IO_L50N_M1UDQSN_1
IO_L74P_AWAKE_1
IO_L74N_DOUT_BUSY_1
IO_L47N_LDC_M1DQ1_1
IO_L47P_FWE_B_M1DQ0_1
IO_L50P_M1UDQS_1
IO_L53N_VREF_1
IO_L46N_FOE_B_M1DQ3_1
IO_L46P_FCS_B_M1DQ2_1
IO_L42N_GCLK6_TRDY1_M1LDM_1
IO_L51N_M1DQ13_1
IO_L52N_M1DQ15_1
IO_L30P_A21_M1RESET_1
IO_L30N_A20_M1A11_1
IO_L32P_A17_M1A8_1
IO_L32N_A16_M1A9_1
IO_L34P_A13_M1WE_1
IO_L34N_A12_M1BA2_1
IO_L36P_A9_M1BA0_1
IO_L39P_M1A3_1
IO_L39N_M1ODT_1
IO_L40P_GCLK11_M1A5_1
IO_L40N_GCLK10_M1A6_1
IO_L53P_1
IO_L61P_1
IO_L61N_1
2
2
U5-2
U5-2
XC6SLX9CSG324
XC6SLX9CSG324
Title
Title
Title
Size
Size
Size
Date:
Date:
Date:
National Semiconductor, Santa Clara, CA 95052
National Semiconductor, Santa Clara, CA 95052
National Semiconductor, Santa Clara, CA 95052
B
B
B
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
DGND
2010 National Semiconductor
2010 National Semiconductor
2010 National Semiconductor
Document Number
Document Number
Document Number
SPIO4 FPGA SRAM & Configuration Intrfc
SPIO4 FPGA SRAM & Configuration Intrfc
SPIO4 FPGA SRAM & Configuration Intrfc
Wednesday, November 17, 2010
Wednesday, November 17, 2010
Wednesday, November 17, 2010
C47
C47
1.0uF
1.0uF
E17
G15
J14
J17
M15
R17
870600474-001
870600474-001
870600474-001
3p3V
C40
C40
0.1uF
0.1uF
C41
C41
0.1uF
0.1uF
C42
C42
0.1uF
0.1uF
Sheet
Sheet
Sheet
1
1
C43
C43
0.1uF
0.1uF
5
5
5
C44
C44
0.1uF
0.1uF
of
of
of
3p3V
DGND
12
12
12
C45
C45
10uF
10uF
Rev
Rev
Rev
2.0
2.0
2.0
D
C
B
A