NAU8812EVB Nuvoton Technology Corporation of America, NAU8812EVB Datasheet - Page 20
NAU8812EVB
Manufacturer Part Number
NAU8812EVB
Description
BOARD EVAL FOR NAU8812
Manufacturer
Nuvoton Technology Corporation of America
Series
emPowerAudio™r
Datasheet
1.NAU8812EVB.pdf
(109 pages)
Specifications of NAU8812EVB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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When the associated control bit is set logic = 1, the MIC- pin is connected to a resistor of approximately 30kΩ which
is tied to VREF. The purpose of the tie to VREF is to reduce any pop or click sound by keeping the DC level of the
MIC- pin close to VREF at all times. It is important for a system designer to know that the MIC-input impedance
varies as a function of the selected PGA gain. This is normal and expected for a difference amplifier type topology.
The above table gives the nominal resistive impedance values for this input over the possible gain range. Impedance
for specific gain values not listed in this table can be estimated through interpolation between listed values.
The PGA amplification is common to all three input pins MIC-, MIC+, AUX, and enabled by PGAEN[2] address
(0x02). It has a range of -12dB to +35.25dB in 0.75dB steps, controlled by PGAGAIN[5:0] address (0x2D). Input
PGA gain will not be used when ALC is enabled using ALCEN[8] address (0x20).
The boost stage has three inputs connected to the PGA Boost Mixer. All three inputs can be individually connected
or disconnected from the PGA Boost Mixer. The boost stage can be enabled by setting BSTEN[4] address (0x02) to
HIGH. The following figure shows the PGA Boost stage.
emPowerAudio
Datasheet Revision 2.0
0x2D
Addr
0x20
12.1.3.
ALCEN
Bit 8
12.1.2.3.
0
™
PGA Boost Stage
PGAZC
Bit 7
Table 5: Registers associated with ALC and Input PGA Gain Control
0
PGA Gain Control
Output from
Output from
AUX stage
PGA Gain
MIC+
Pin
PGAMT
Bit 6
0
Figure 7: Boost Stage Block Diagram
Bit5
Page 20 of 109
ALCMXGAIN[2:0]
PGABST[8]
(0x2F)
PMICBSTGAIN[6:4]
AUXBSTGAIN[2:0]
Bit 4
(0x2F)
(0x2F)
PGAMT[6]
(0x2D)
Bit 3
PGAGAIN[5:0]
Bit 2
To ADC
ALCMNGAIN[2:0]
Bit 1
NAU8812
January 2011
Bit 0
Default
0x010
0x038
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