NAU8812EVB Nuvoton Technology Corporation of America, NAU8812EVB Datasheet - Page 39

• Manufacturer Part Number: NAU8812EVB
• Description: BOARD EVAL FOR NAU8812
• Manufacturer: Nuvoton Technology Corporation of America
• Series: emPowerAudio™r

Specifications of NAU8812EVB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NAU8812
input or output pin. The goal to reduce pops and clicks is to insure that the charge voltage on these capacitors does
not change suddenly at any time.
When an input or output is in a not-used operating condition, it is desirable to keep the DC voltage on that pin at the
same voltage level as the DC level of the used operating condition. This is accomplished using special internal DC
voltage sources that are at the required DC values. When an input or output is in the not-used condition, it is
connected to the correct internal DC voltage as not to have a pop or click. This type of connection is known as a “tie-
off” condition.
Two internal DC voltage sources are provided for making tie-off connections. One DC level is equal to the VREF
voltage value, and the other DC level is equal to 1.5x the VREF value. All inputs are always tied off to the VREF
voltage value. Outputs will automatically be tied to either the VREF voltage value or to the 1.5xVREF value,
depending on the value of the “boost” control bit for that output. That is to say, when an output is set to the 1.5x gain
condition, then that same output will automatically use the 1.5xVREF value for tie-off in the not-used condition. The
input pull-ups are connected to IOBUFEN[2] address (0x01) buffer with a voltage source (VREF). The output pull-ups
can be connected two different buffers depending on the voltage source. IOBUFEN[2] address (0x01) buffer is
enabled if the voltage source is (VREF) and DCBUFEN[8] address (0x01) buffer is enabled if the voltage source is
(1.5 x VREF). IOBUFEN[2] address (0x01) buffer is shared between input and output pins.
To conserve power, these internal voltage buffers may be enabled/disabled using control register settings. To better
manage pops and clicks, there is a choice of impedance of the tie-off connection for unused outputs. The nominal
values for this choice are 1kΩ and 30kΩ. The low impedance value will better maintain the desired DC level in the
case when there is some leakage on the output capacitor or some DC resistance to ground at the NAU8812 output
pin. A tradeoff in using the low-impedance value is primarily that output capacitors could change more suddenly
during power-on and power-off changes.
Automatic internal logic determines whether an input or output pin is in the used or un-used condition. This logic
function is always active. An output is determined to be in the un-used condition when it is in the disabled unpowered
condition, as determined by the power management registers. An input is determined to be in the un-used condition
when all internal switches connected to that input are in the “open” condition.
12.7. GENERAL PURPOSE I/O
The CSb/GPIO pin can be configured in two ways, chip select for SPI interface and general purpose GPIO.
Therefore, the general-purpose configuration is only available in the 2-Wire interface mode, which is configured by
setting GPIOSEL[2:0] address (0x08) to 001 – 101. “000” configures the pin to be a chip select for SPI mode. The
CSb/GPIO pin is not available in the SPI interface mode. When the pin is configured as an input, it can be used as
chip select signal for SPI interface or for jack detect. When the pin is configured as output, it can be used for
signaling analog mute, temperature alert, PLL frequency output, and PLL frequency lock. The CSb/GPIO pin can
also output the master clock through a PLL or directly. The path also included a divider for different clocks needed in
the system. Note that SCLKEN must be enabled when using the Jack Detect function.
emPowerAudio
™
Datasheet Revision 2.0
Page 39 of 109
January 2011