NAU8812EVB Nuvoton Technology Corporation of America, NAU8812EVB Datasheet - Page 49

• Manufacturer Part Number: NAU8812EVB
• Description: BOARD EVAL FOR NAU8812
• Manufacturer: Nuvoton Technology Corporation of America
• Series: emPowerAudio™r

Specifications of NAU8812EVB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

All 2-Wire interface operations must begin with a START condition, which is a HIGH to LOW transition of SDIO while
SCLK is HIGH. All 2-Wire and all interface operations are terminated by a STOP condition, which is a LOW to HIGH
transition of SDIO while SCLK is HIGH. A STOP condition at the end of a read or write operation places the device in
standby mode. An acknowledge (ACK), is a software convention used to indicate a successful data transfer. The
transmitting device, either master or slave, releases the SDIO bus after transmitting eight bits. During the ninth clock
cycle, the receiver pulls the SDIO line LOW to acknowledge the reception of the eight bits of data.
Following a START condition, the master must output a device address byte. The 7-MSB bits “0011010” are the
device address. The LSB of the device address byte is the R/W bit and defines a read (R/W = 0) or write (R/W = 1)
operation. When this, R/W, bit is a “1”, then a read operation is selected and when “0” the device selects a write
operation. The device outputs an acknowledge LOW for a correct device address and HIGH for an incorrect device
address on the SDIO pin.
A Write operation consists of a two-byte instruction followed by one or more Data Bytes. A Write operation requires a
START condition, followed by a valid device address byte, a valid control address byte, data byte(s), and a STOP
condition. After each three bytes sequence, the NAU8812 responds with an ACK and the 2-Wire interface enters a
standby state.
emPowerAudio
Datasheet Revision 2.0
Figure 25: Valid START Condition
12.9.2.2.
12.9.2.1.
SCLK
SDIO
™
START
A6
D7
0
2-WIRE Protocol Convention
2-WIRE Write Operation
Figure 28: Slave Address Byte, Control Address Byte, and Data Byte
D6
A5
0
A4
D5
1
Figure 26: Valid Acknowledge
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A3
D4
Receive
Transmit
1
SDIO
SDIO
SCLK
D3
A2
0
Clock
ACK
9
th
A1
D2
1
D1
A0
0
Figure 27: Valid STOP Condition
Write - D8
Read - 0
R/W
D0
SCLK
SDIO
NAU8812
January 2011
Device
Address Byte
Control
Address Byte
Data Byte
STOP