NAU8812EVB Nuvoton Technology Corporation of America, NAU8812EVB Datasheet - Page 51

• Manufacturer Part Number: NAU8812EVB
• Description: BOARD EVAL FOR NAU8812
• Manufacturer: Nuvoton Technology Corporation of America
• Series: emPowerAudio™r

Specifications of NAU8812EVB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NAU8812 only uses the Left channel to transfer data in normal mode. It supports an independent digital interface for
voice and audio. The digital interface is used to input digital data to the DAC, or output digital data from the ADC.
The digital interface can be configured to Master mode or Slave mode.
Master mode is configured by setting CLKIOEN[0] address (0x06) bit to HIGH. The main clock (MCLK) of the digital
interface is provided from an external clock either from a crystal oscillator or from a microcontroller. With an
appropriate MCLK, the device generates bit clock (BCLK) and frame sync (FS) internally in the master mode. By
generating the bit clock and frame sync internally, the NAU8812 has full control of the data transfer.
Slave mode is configured by setting CLKIOEN[0] address (0x06) bit to LOW. In this mode, an external controller has
to supply the bit clock and the frame sync. The NAU8812 uses ADCOUT, DACIN, FS, and BCLK pins to control the
digital interface. Care needs to be exercised when designing a system to operate the NAU8812 in this mode as the
relationship between the sample rate, bit clock, and frame sync needs to be controlled by other controller. In both
modes of operation, the internal MCLK and MCLK prescalers determine the sample rate for the DAC and ADC.
The output state of the ADCOUT pin by default is pulled-low. Depending on the application, the output can be
configured to be Hi-Z, pull-low, pull-high, Low or High. To configure the output, three different bits have to be set.
First the output switched to the mask by setting PUDOEN[5] address (0x3C), then the mask has to be enabled be
setting PUDPE[4] address (0x3C) and finally output state select pulled up or down by PUDPS[3] address (0x3C). Six
different audio formats are supported by NAU8812 with MSB first and they are as follows.
emPowerAudio
Datasheet Revision 2.0
0x3B
0x3C PCMTSEN
Addr
0x04
0x06
12.10. DIGITAL AUDIO INTERFACES
BCLKP
CLKM
D8
™
Addr: (0x04)
AIFMT[4]
FSP
TRI
0
0
0
1
1
1
D7
MCLKSEL[2:0]
PCM8BIT PUDOEN
D6
Addr: (0x04)
WLEN[1:0]
AIFMT[3]
Table 28: Audio Interface Control Registers
0
0
1
0
1
1
Table 27: Standard Interface modes
D5
Page 51 of 109
PCMTSEN[8]
Addr: (0x3C)
TSLOT[8:0]
PUDPE
D4
0
0
0
0
0
1
AIFMT[1:0]
BCLKSEL[2:0]
PUDPS
Addr: (0x3C)
D3
PCMB[1]
1
0
0
0
0
0
DACPHS ADCPHS
LOUTR
D2
PCM B
Right Justified
Left Justified
I
PCM A
PCM Time Slot
2
S
PCM Mode
PCMB
D1
0
NAU8812
January 2011
TSLOT[9:8] 0x000
CLKIOEN
D0
0
Default
0x050
0x140
0x000