ISL9208EVAL2Z Intersil, ISL9208EVAL2Z Datasheet - Page 22

• Manufacturer Part Number: ISL9208EVAL2Z
• Description: EVAL BOARD 2 FOR ISL9208
• Manufacturer: Intersil

Specifications of ISL9208EVAL2Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

User Flags
The ISL9208 contains four flags in the register area that the
microcontroller can use for general purpose indicators.
These bits are designated UFLG3, UFLG2, UFLG1, and
UFLG0. The microcontroller can set or reset these bits by
writing into the appropriate register.
The user flag bits are battery backed up, so the contents
remain even after exiting a sleep mode. However, if the
microcontroller sets the POR bit to force a power on reset, all
of the user flags will also be reset. In addition, if the voltage
on cell1 ever drops below the POR voltage, the contents of
the user flags (as well as all other register values) could be
lost.
Serial Interface
INTERFACE CONVENTIONS
The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the slave.
The master always initiates data transfers, and provides the
clock for both transmit and receive operations. Therefore,
the ISL9208 devices operate as slaves in all applications.
When sending or receiving data, the convention is the most
significant bit (MSB) is sent first. So, the first address bit sent
is bit 7.
CLOCK AND DATA
Data states on the SDA line can change only while SCL is
LOW. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions. See Figure 9.
START CONDITION
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
start condition and will not respond to any command until
this condition has been met. See Figure 10.
STOP CONDITION
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the device
into the Standby power mode after a read sequence. A stop
condition is only issued after the transmitting device has
released the bus. See Figure 10.
ACKNOWLEDGE
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, releases the bus after transmitting eight
bits. During the ninth clock cycle, the receiver pulls the SDA
line LOW to acknowledge that it received the eight bits of
data. See Figure 11.
22
ISL9208
The device responds with an acknowledge after recognition
of a start condition and the correct slave byte. If a write
operation is selected, the device responds with an
acknowledge after the receipt of each subsequent eight bits.
The device acknowledges all incoming data and address
bytes, except for the slave byte when the contents do not
match the device’s internal slave address.
In the read mode, the device transmits eight bits of data,
releases the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the device will
continues to transmit data. The device terminates further
data transmissions if an acknowledge is not detected. The
master must then issue a stop condition to return the device
to Standby mode and place the device into a known state
.
FROM RECEIVER
SCL
SDA
TRANSMITTER
DATA OUTPUT
DATA OUTPUT
SDA
SCL
FIGURE 11. ACKNOWLEDGE RESPONSE FROM
SCL FROM
FIGURE 9. VALID DATA CHANGES ON I
MASTER
FROM
FIGURE 10. I
RECEIVER
STABLE
START
DATA
START
2
C START AND STOP BITS
1
CHANGE
DATA
STABLE
DATA
8
STOP
ACKNOWLEDGE
2
C BUS
November 2, 2007
9
FN6446.1