SERDESUR-65USB/NOPB National Semiconductor, SERDESUR-65USB/NOPB Datasheet
SERDESUR-65USB/NOPB
Specifications of SERDESUR-65USB/NOPB
Related parts for SERDESUR-65USB/NOPB
SERDESUR-65USB/NOPB Summary of contents
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... DS90UR906Q (Des) is offered in a 60-pin LLP package. They are specified over the automotive AEC-Q100 grade 2 tem- perature range of -40°C to +105°C. Applications Diagram TRI-STATE ® registered trademark of National Semiconductor Corporation. © 2011 National Semiconductor Corporation DS90UR905Q/DS90UR906Q Features ■ 5 – 65 MHz PCLK support (140 Mbps – 1.82 Gbps) ■ ...
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Block Diagrams www.national.com 30102028 2 30102029 ...
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Ordering Information NSPN Package Description DS90UR905QSQE NOPB 48–pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch DS90UR905QSQ NOPB 48–pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch DS90UR905QSQX NOPB 48–pin LLP, 7.0 X 7.0 X 0.8 ...
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DS90UR905Q Serializer Pin Descriptions Pin Name Pin # I/O, Type LVCMOS Parallel Interface R[7:0] 34, 33, 32, 29, I, LVCMOS 28, 27, 26 pull-down G[7:0] 42, 41, 40, 39, I, LVCMOS 38, 37, 36 pull-down B[7:0] ...
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Pin Name Pin # I/O, Type BISTEN 31 I, LVCMOS w/ pull-down RES[2:0] 18, 16 LVCMOS w/ pull-down FPD-Link II Serial Interface DOUT LVDS DOUT LVDS Power and Ground VDDL 7 Power VDDP 14 ...
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DS90UR906Q Pin Diagram www.national.com Deserializer - DS90UR906Q — Top View 6 30102020 ...
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DS90UR906Q Deserializer Pin Descriptions Pin Name Pin # I/O, Type LVCMOS Parallel Interface R[7:0] 33, 34, 35, I, STRAP, 36, 37, 39, O, LVCMOS 40, 41 G[7:0] 20, 21, 22, I, STRAP, 23, 25, 26, O, LVCMOS 27, 28 B[7:0] ...
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Pin Name Pin # I/O, Type OS_PCLK 11 [B5] STRAP I, LVCMOS w/ pull-down OS_DATA 14 [B3] STRAP I, LVCMOS w/ pull-down OP_LOW 42 PASS STRAP I, LVCMOS w/ pull-down OSS_SEL 17 [B2] STRAP I, LVCMOS w/ pull-down RFB 18 ...
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Pin Name Pin # I/O, Type NC 1, 15, 16, 30, 31, 45, 46, 60 FPD-Link II Serial Interface RIN LVDS RIN LVDS CMF 51 I, Analog CMLOUTP 52 O, LVDS CMLOUTN 53 O, LVDS Power ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage – V (1.8V) DDn Supply Voltage – V DDIO LVCMOS I/O Voltage −0.3V to +(VDDIO + 0.3V) Receiver Input Voltage Driver Output Voltage ...
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Serializer DC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter LVCMOS INPUT DC SPECIFICATIONS V High Level Input Voltage IH V Low Level Input Voltage IL I Input Current IN LVDS DRIVER DC SPECIFICATIONS ...
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Deserializer DC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter 3.3 V I/O LVCMOS DC SPECIFICATIONS – High Level Input Voltage IH V Low Level Input Voltage IL I Input Current IN ...
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Symbol Parameter LVDS RECEIVER DC SPECIFICATIONS Differential Input Threshold High V TH Voltage Differential Input Threshold Low V TL Voltage Common Mode Voltage, Internal BIAS I Input Current IN R Internal Termination Resistor T CMLOUTP/N DRIVER OUTPUT ...
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Serializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter t Ser Output Low-to-High LHT Transition Time, Figure 3 t Ser Output High-to-Low HLT Transition Time, Figure 3 t Input Data - Setup Time, DIS ...
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Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter t PCLK Output Period RCP t PCLK Output Duty Cycle RDC t LVCMOS CLH Low-to-High Transition Time, Figure 10 t LVCMOS CHL High-to-Low Transition Time, ...
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Symbol Parameter BIST Mode t BIST PASS Valid Time, PASS BISTEN = 1, Figure 17 SSCG Mode f Spread Spectrum DEV Clocking Deviation Frequency f Spread Spectrum MOD Clocking Modulation Frequency Recommended Timing for the Serial Control Bus Over 3.3V ...
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DC and AC Serial Control Bus Characteristics Over 3.3V supply and temperature ranges unless otherwise specified. Symbol Parameter V Input High Level IH V Input Low Level Voltage IL V Input Hysteresis HY V Output Low Level Voltage, OL (Note ...
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AC Timing Diagrams and Test Circuits FIGURE 4. Serializer Input PCLK Waveform and Set and Hold Times www.national.com FIGURE 1. Serializer Test Circuit FIGURE 2. Serializer Output Waveforms FIGURE 3. Serializer Output Transition Times 18 30102046 30102030 30102047 30102031 ...
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FIGURE 5. Serializer Lock Time FIGURE 6. Serializer Disable Time FIGURE 7. Serializer Latency Delay 19 30102048 30102049 30102010 www.national.com ...
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FIGURE 8. Serializer Output Jitter FIGURE 9. Checkerboard Data Pattern FIGURE 10. Deserializer LVCMOS Transition Times FIGURE 11. Deserializer Delay – Latency 20 30102050 30102032 30102005 30102011 ...
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FIGURE 12. Deserializer Disable Time (OSS_SEL = 0) FIGURE 13. Deserializer PLL Lock Times and PDB TRI-STATE Delay FIGURE 14. Deserializer Output Data Valid (Setup and Hold) Times with SSCG = Off 21 30102013 30102014 30102035 www.national.com ...
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FIGURE 15. Deserializer Output Data Valid (Setup and Hold) Times with SSCG = On www.national.com FIGURE 16. Receiver Input Jitter Tolerance FIGURE 17. BIST PASS Waveform 22 30102034 30102016 30102052 ...
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FIGURE 18. Serial Control Bus Timing Diagram 23 30102036 www.national.com ...
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Functional Description The DS90UR905Q / DS90UR906Q chipset transmits and re- ceives 27-bits of data (24-high speed color bits and 3 low speed video control signals) over a single serial FPD-Link II pair operating at 140Mbps to 1.82Gbps. The serial stream ...
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SERIALIZER FUNCTIONAL DESCRIPTION The Ser converts a wide parallel input bus to a single serial output data stream, and also acts as a signal generator for the chipset Built In Self Test (BIST) mode. The device can be configured via ...
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Optional BIST Mode Please see the following section on the chipset BIST mode for details. DESERIALIZER FUNCTIONAL DESCRIPTION The Des converts a single input serial data stream to a wide parallel output bus, and also provides a signal check for ...
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TABLE 7. SSCG Configuration (LF_MODE = H) — Des Output SSC[3:0] Inputs LH_MODE = MHz) SSC3 SSC2 ...
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TABLE 8. OSS_SEL and PDB Configuration — Des Outputs INPUTS Serial PDB Input X L Static H Static H Active H *NOTE — If pin is strapped HIGH, output will be pulled up INPUTS Embedded PCLK NOTE * Present ≠ ...
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FIGURE 24. Des Outputs with Output State Select High (OSS_SEL = H) TABLE 10. OSC_SEL (Oscillator) Configuration OSC_SEL[2:0] INPUTS OSC_SEL2 OSC_SEL1 PCLK Oscillator Output ...
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FIGURE 25. Des Outputs with Output State High and PCLK Output Oscillator Option Enabled Des — OP_LOW — Optional The OP_ LOW feature is used to hold the LVCMOS outputs (except the LOCK output LOW state. The user ...
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Des — Pixel Clock Edge Select (RFB) The RFB pin determines the edge that the data is strobed on. If RFB is High, output data is strobed on the Rising edge of the PCLK. If RFB is Low, data is ...
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Des — Control Signal Filter — Optional The Des provides an optional Control Signal (VS, HS, DE) filter that monitors the three video control signals and elimi- nates any pulses that are PCLKs wide. Control signals must ...
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FIGURE 28. BIST Mode Flow Diagram FIGURE 29. BIST Waveforms BER Calculations It is possible to calculate the approximate Bit Error Rate (BER). The following is required: • Pixel Clock Frequency (MHz) • BIST Duration (seconds) • BIST test ...
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Optional Serial Bus Control The Ser and Des may also be configured by the use of a serial control bus that is I2C protocol compatible. By default, the I2C reg_0x00'h is set to 00'h and all configuration is set by ...
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TABLE 14. SERIALIZER — Serial Bus Control Registers ADD ADD Register Name Bit(s) (dec) (hex Ser Config 3 Device De-Emphasis 7:5 Control 4 3:0 ...
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TABLE 15. DESERIALIZER — Serial Bus Control Registers ADD ADD Register Name Bit(s) (dec) (hex Des Config 1 3 Slave ID 6 Des Features 1 5:4 2:0 www.national.com R/W Defa Function ult (bin) 7 ...
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ADD ADD Register Name Bit(s) (dec) (hex Des Features 2 7 CMLOUT 7 Config 6:0 R/W Defa Function Description ult (bin) R/W 000 EQ Gain 000: ~1.625 dB 001: ~3.25 dB 010: ~4.87 dB ...
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Applications Information DISPLAY APPLICATION The DS90UR905Q/906Q chipset is intended for interface be- tween a host (graphics processor) and a Display. It supports an 24-bit color depth (RGB888) and up to 1024 X 768 display formats RGB888 application, 24 ...
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Figure 35 shows a typical application of the DS90UR906Q Des in Pin/STRAP control mode for a 65 MHz 24-bit Color Display Application. The LVDS inputs utilize 100 nF coupling capacitors to the line and the Receiver provides internal ter- mination. ...
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POWER UP REQUIREMENTS AND PDB PIN The VDD (V and V ) supply ramp should be faster than DDn DDIO 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on the PDB pin is needed ...
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ALTERNATE COLOR / DATA MAPPING Color Mapped data Pin names are provided to specify a rec- ommended mapping for 24-bit Color Applications. Seven [7] is assumed to be the MSB, and Zero [0] is assumed to be the LSB. While ...
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Revision History • 2/01/2010 • DS90UR905Q DATASHEET LIMITS HAVE BEEN UPDATED PER CHARACTERIZATION RESULT AND ARE THE FINAL LIMITS • Updated TABLE 12: deleted ID[x] Address 7'b 110 1000 (h'68) (8'b 1101 0000 (h'D0)) • Updated TABLE 13: deleted ID[x] ...
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Physical Dimensions inches (millimeters) unless otherwise noted 48–pin LLP Package (7 7 0.8 mm, 0.5 mm pitch) 60–pin LLP Package (9 9 0.8 mm, 0.5 mm pitch) NS Package Number SQA48A NS ...
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... For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock and Timing www.national.com/timing Data Converters www.national.com/adc Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www ...