SERDESUR-65USB/NOPB National Semiconductor, SERDESUR-65USB/NOPB Datasheet - Page 9

• Manufacturer Part Number: SERDESUR-65USB/NOPB
• Description: EVAL BOARD FOR DS90UR905
• Manufacturer: National Semiconductor

Specifications of SERDESUR-65USB/NOPB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Name
NC
FPD-Link II Serial Interface
RIN+
RIN-
CMF
CMLOUTP
CMLOUTN
Power and Ground
VDDL
VDDIR
VDDR
VDDSC
VDDPR
VDDCMLO
VDDIO
GND
NOTE: 1 = HIGH, 0 = LOW
The VDD (V
on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
DDn
30, 31, 45,
13, 24, 38
1, 15, 16,
and V
46, 60
43, 55
Pin #
4, 58
DAP
49
50
51
52
53
29
48
57
54
DDIO
) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor
I/O, Type
I, Analog
O, LVDS
O, LVDS
I, LVDS
I, LVDS
Ground
Power
Power
Power
Power
Power
Power
Power
Description
Not Connected
Leave pin open (float)
True Input. The input must be AC Coupled with a 100 nF capacitor.
Inverting Input. The input must be AC Coupled with a 100 nF capacitor.
Common-Mode Filter
VCM center-tap is a virtual ground which may be ac-coupled to ground to increase receiver
common mode noise immunity. Recommended value is 0.1μF or higher.
Test Monitor Pin — EQ Waveform
NC or connect to test point. Requires Serial Bus Control to enable.
Test Monitor Pin — EQ Waveform
NC or connect to test point. Requires Serial Bus Control to enable.
Logic Power, 1.8 V ±5%
Input Power, 1.8 V ±5%
RX High Speed Logic Power, 1.8 V ±5%
SSCG Power, 1.8 V ±5%
PLL Power, 1.8 V ±5%
RX High Speed Logic Power, 1.8 V ±5%
LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10% (V
DAP is the large metal contact at the bottom side, located at the center of the LLP package.
Connected to the ground plane (GND) with at least 9 vias.
9
DDIO
)
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