SERDESUR-65USB/NOPB National Semiconductor, SERDESUR-65USB/NOPB Datasheet - Page 7

• Manufacturer Part Number: SERDESUR-65USB/NOPB
• Description: EVAL BOARD FOR DS90UR905
• Manufacturer: National Semiconductor

Specifications of SERDESUR-65USB/NOPB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Name
LVCMOS Parallel Interface
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
LOCK
PASS
Control and Configuration — STRAP PINS
For a High State, use a 10 kΩ pull up to V
power-up and set device configuration. Pin Number listed along with shared RGB Output name in square brackets.
CONFIG[1:0]
LF_MODE
DS90UR906Q Deserializer Pin Descriptions
33, 34, 35,
36, 37, 39,
20, 21, 22,
23, 25, 26,
12, 14, 17,
9, 10, 11,
10 [B6],
12 [B4]
40, 41
27, 28
18, 19
9 [B7]
Pin #
32
42
8
7
6
5
w/ pull-down
w/ pull-down
O, LVCMOS
O, LVCMOS
O, LVCMOS
O, LVCMOS Horizontal Sync Output
O, LVCMOS Vertical Sync Output
O, LVCMOS Data Enable Output
O, LVCMOS Pixel Clock Output
O, LVCMOS LOCK Status Output
O, LVCMOS PASS Output (BIST Mode)
I, LVCMOS
I, LVCMOS
I, STRAP,
I, STRAP,
I, STRAP,
I/O, Type
STRAP
STRAP
DDIO
Description
RED Parallel Interface Data Output Pins (MSB = 7, LSB = 0)
In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See
pins are inputs during power-up (See STRAP Inputs).
GREEN Parallel Interface Data Output Pins (MSB = 7, LSB = 0)
In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See
pins are inputs during power-up (See STRAP Inputs).
BLUE Parallel Interface Data Output Pins (MSB = 7, LSB = 0)
In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See
pins are inputs during power-up (See STRAP Inputs).
In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See
control signal pulse width must be 3 PCLKs or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00). The signal is limited to
2 transitions per 130 PCLKs.
In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See
control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width is 130
PCLKs.
In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See
control signal pulse width must be 3 PCLKs or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00). The signal is limited to
2 transitions per 130 PCLKs.
In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See
edge set by RFB function.
LOCK = 1, PLL is Locked, outputs are active LOCK = 0, PLL is unlocked, RGB[7:0], HS,
VS, DE and PCLK output states are controlled by OSS_SEL (See
as Link Status or to flag when Video Data is active (ON/OFF).
PASS = 1, error free transmission
PASS = 0, one or more errors were detected in the received payload
Route to test point for monitoring, or leave open if unused.
Operating Modes — Pin or Register Control
These pins determine the DS90UR906’s operating mode and interfacing device.
CONFIG[1:0] = 00: Interfacing to DS90UR905, Control Signal Filter DISABLED
CONFIG[1:0] = 01: Interfacing to DS90UR905, Control Signal Filter ENABLED
CONFIG[1:0] = 10: Interfacing to DS90UR241
CONFIG[1:0] = 11: Interfacing to DS90C241
SSCG Low Frequency Mode — Pin or Register Control
Only required when SSCG is enabled, otherwise LF_MODE condition is a DON’T CARE
(X).
LF_MODE = 1, SSCG in low frequency mode (PCLK = 5-20 MHz)
LF_MODE = 0, SSCG in high frequency mode (PCLK = 20-65 MHz)
; for a Low State, the IO includes an internal pull down. The STRAP pins are read upon
7
Table
Table
Table
Table
8). May be used
Table
Table
Table
Table
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8). These
8). These
8). These
8). Video
8). Video
8). Video
8). Strobe