KDC5512HEVALZ Intersil, KDC5512HEVALZ Datasheet - Page 22

• Manufacturer Part Number: KDC5512HEVALZ
• Description: DAUGHTER CARD FOR KDC5512
• Manufacturer: Intersil

Specifications of KDC5512HEVALZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Mapping of the input voltage to the various data formats is
shown in Table 5.
–Full Scale 000 00 000 00 00 100 00 000 00 00 000 00 000 00 00
–Full Scale
+Full Scale
+Full Scale 111 11 111 11 11
VOLTAGE OFFSET BINARY
Mid–Scale 100 00 000 00 00 000 00 000 00 00 110 00 000 00 00
+ 1LSB
– 1LSB
SCLK
SDIO
INPUT
CSB
SCLK
SDIO
CSB
TABLE 5. INPUT VOLTAGE TO OUTPUT CODE MAPPING
FIGURE 32. GRAY CODE TO BINARY CONVERSION
GRAY CODE
BINARY
000 00 000 00 01 100 00 000 00 01 000 00 000 00 01
111 11 111 11 10
11
11
A0
R/W
10
10
22
A1
011 11 111 11 10 100 00 000 00 01
011 11 111 111 1 100 00 000 00 00
W1
COMPLEMENT
9
TWO’S
9
A2
W0
• • • •
• • • •
• • • •
• • • •
A11
A12
FIGURE 33. MSB-FIRST ADDRESSING
FIGURE 34. LSB-FIRST ADDRESSING
A12
A11
GRAY CODE
1
1
W0
A10
0
KAD5512HP
0
W1
A1
R/W
A0
Serial Peripheral Interface
A serial peripheral interface (SPI) bus is used to facilitate
configuration of the device and to optimize performance. The
SPI bus consists of chip select (CSB), serial clock (SCLK)
serial data input (SDI) and serial data input/output (SDIO).
The maximum SCLK rate is equal to the ADC sample rate
(f
divided by 66 for reads. At f
SCLK is 15.63MHz for writing and 3.79MHz for read
operations. There is no minimum SCLK rate.
The following sections describe various registers that are
used to configure the SPI or adjust performance or functional
parameters. Many registers in the available address space
(0x00 to 0xFF) are not defined in this document. Additionally,
within a defined register there may be certain bits or bit
combinations that are reserved. Undefined registers and
undefined values within defined registers are reserved and
should not be selected. Setting any reserved register or value
may produce indeterminate results.
SAMPLE
D0
D7
D1
) divided by 16 for write operations and f
D6
D2
D5
D3
D4
SAMPLE
D4
D3
D5
D2
= 250MHz, maximum
D6
D1
D7
D0
October 1, 2009
SAMPLE
FN6808.3