KDC5512HEVALZ Intersil, KDC5512HEVALZ Datasheet - Page 27

• Manufacturer Part Number: KDC5512HEVALZ
• Description: DAUGHTER CARD FOR KDC5512
• Manufacturer: Intersil

Specifications of KDC5512HEVALZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Test
The KAD5512HP can produce preset or user defined
patterns on the digital outputs to facilitate in-situ testing. A
static word can be placed on the output bus, or two different
words can alternate. In the alternate mode, the values
defined as Word 1 and Word 2 (as shown in Table 15) are
set on the output bus on alternating clock phases. The test
mode is enabled asynchronously to the sample clock,
therefore several sample clock cycles may elapse before the
data is present on the output bus.
ADDRESS 0XC0: TEST_IO
Bits 7:6 User Test Mode
The four LSBs in this register (Output Test Mode) determine
the test pattern in combination with registers 0xC2 through
0xC5. Refer to Table 16.
These bits set the test mode to static (0x00) or alternate
(0x01) mode. Other values are reserved.
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KAD5512HP
ADDRESS 0XC2: USER_PATT1_LSB
ADDRESS 0XC3: USER_PATT1_MSB
These registers define the lower and upper eight bits,
respectively, of the first user-defined test word.
ADDRESS 0XC4: USER_PATT2_LSB
ADDRESS 0XC5: USER_PATT2_MSB
These registers define the lower and upper eight bits,
respectively, of the second user-defined test word.
VALUE
0000
0001
0010
0011
0100
0101
0110
1000
0111
TABLE 15. OUTPUT TEST MODES
Negative Full-Scale
Positive Full-Scale
OUTPUT TEST
Checkerboard
User Pattern
0xC0[3:0]
Reserved
Reserved
One/Zero
Midscale
MODE
Off
user_patt1
WORD 1
0xAAAA
0xFFFF
0xFFFF
0x8000
0x0000
N/A
N/A
October 1, 2009
user_patt2
WORD 2
0x5555
0x0000
N/A
N/A
N/A
N/A
N/A
FN6808.3