ISL8206MEVAL1Z Intersil, ISL8206MEVAL1Z Datasheet - Page 10

• Manufacturer Part Number: ISL8206MEVAL1Z
• Description: EVAL BOARD 1 FOR ISL8206
• Manufacturer: Intersil

Specifications of ISL8206MEVAL1Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reference Circuitry For General
Applications
Applications Information
The typical ISL8204M, ISL8206M application schematic
for input voltage +5V or +12V is shown in Figure 15.
External component selection is primarily determined by
the maximum load current and input/output voltage.
Programming the Output Voltage
The ISL8204M, ISL8206M has an internal 0.6V ±1.5%
reference voltage. Programming the output voltage
requires a dividing resistor (R
be calculated as shown in Equation 1:
V
1. Single Power Supply
2. Separated Power Supply
FIGURE 16. WIDE INPUT VOLTAGE APPLICATION
OUT
R
R
FB
FIGURE 15. TYPICAL APPLICATION SCHEMATIC
Figure 15 shows the ISL8204M, ISL8206M
application schematic for input voltage +5V or
+12V. The PVCC pin can connect to the input
supply directly.
Figure 16 shows the ISL8204M, ISL8206M
application schematic for wide input voltages from
+1V to +20V. The P
+5V/+12V or +6.5V to 14.4V.
FB
=
R
R
SET-EX
0.6
SET-EX
×
⎛
⎝
1
SCHEMATIC
(+6.5V to 14.4V)
+
(+5V/+12V)
9.76k
-------------- -
R
FB
COMP/EN
ISET
CO M P/EN
ISL8204M, ISL8206M
FB
ISET
FB
ISL8204M , ISL8206M
or
⎞
⎠
PVCC
PGND
PVCC
PG ND
VCC
P
10
VCC
C
supply can source
C
FB
PHASE
PVCC
PHASE
PVCC
VOUT
VO UT
). The output voltage can
VIN
VIN
(+1V to +20V)
ISL8204M, ISL8206M
C
(+5V/+12V)
C
C
C
OUT
IN
IN
OUT
V
V
OUT
OUT
V
V
(EQ. 1)
IN
IN
Note: ISL8204M, ISL8206M has integrated 9.76kΩ
resistance into the module (dividing resistor for top
side). The resistance corresponding to different output
voltages is as shown in Table 2:
Initialization (POR and OCP Sampling)
Figure 17 shows a start-up waveform of ISL8204M,
ISL8206M. The power-on-reset (POR) function
continually monitors the bias voltage at the PVCC pin.
Once the rising POR threshold has exceeded 4V (V
nominal), the POR function initiates the overcurrent
protection (OCP) sample and hold operation (while
COMP/EN is ~1V). When the sampling is complete, V
begins the soft-start ramp.
If the COMP/EN pin is held low during power-up, the
initialization will be delayed until the COMP/EN is
released and its voltage rises above the V
Figure 18 and Figure 19 show a typical power-up
sequence in more detail. The initialization starts at T
when either P
is released (after POR). The COMP/EN will be pulled up
by an internal 20µA current source, however, the timing
will not begin until the COMP/EN exceeds the V
point (at T
device, as well as the compensation capacitors, will
determine how quickly the 20µA current source will
charge the COMP/EN pin. With typical values, it should
FIGURE 17. POR AND SOFT-START OPERATION
V
V
V
TABLE 2. RESISTANCE TO OUTPUT VOLTAGES
R
R
R
OUT
OUT
OUT
FB
FB
FB
~4V
1
). The external capacitance of the disabling
VCC
6.49kΩ
1.33kΩ
open
rises above V
0.6V
1.5V
5V
28.7kΩ
4.87kΩ
1.07kΩ
0.8V
1.8V
6V
PORR
, or the COMP/EN pin
3.09kΩ
1.05V
13kΩ
2.5V
ENDIS
December 16, 2010
COMP/EN
trip point.
ENDIS
V
PVCC
9.76kΩ
2.16kΩ
OUT
1.2V
3.3V
FN6999.2
PORR
0
OUT
trip
,