ISL8206MEVAL1Z Intersil, ISL8206MEVAL1Z Datasheet - Page 17

• Manufacturer Part Number: ISL8206MEVAL1Z
• Description: EVAL BOARD 1 FOR ISL8206
• Manufacturer: Intersil

Specifications of ISL8206MEVAL1Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Thermal Vias
A grid of 1.0mm to 1.2mm pitch thermal vias, which
drops down and connects to buried copper plane(s),
should be placed under the thermal land. The vias should
be about 0.3mm to 0.33mm in diameter with the barrel
plated to about 1.0 ounce copper. Although adding more
vias (by decreasing via pitch) will improve the thermal
performance, diminishing returns will be seen as more
and more vias are added. Simply use as many vias as
practical for the thermal land size and your board design
rules allow.
Stencil Pattern Design
Reflowed solder joints on the perimeter I/O lands should
have about a 50µm to 75µm (2mil to 3mil) standoff
height. The solder paste stencil design is the first step in
developing optimized, reliable solder joints. Stencil
aperture size to land size ratio should typically be 1:1. The
aperture width may be reduced slightly to help prevent
solder bridging between adjacent I/O lands. To reduce
solder paste volume on the larger thermal lands, it is
recommended that an array of smaller apertures be used
instead of one large aperture. It is recommended that the
stencil printing area cover 50% to 80% of the PCB layout
pattern. A typical solder stencil pattern is shown in the
Package Outline Drawing L15.15x15 on page 19. The gap
width between pad to pad is 0.6mm. The user should
consider the symmetry of the whole stencil pattern when
designing its pads. A laser cut, stainless steel stencil with
electropolished trapezoidal walls is recommended.
Electropolishing “smooths” the aperture walls resulting in
reduced surface friction and better paste release which
reduces voids. Using a trapezoidal section aperture (TSA)
also promotes paste release and forms a "brick like" paste
deposit that assists in firm component placement. A
0.1mm to 0.15mm stencil thickness is recommended for
this large pitch (1.3mm) QFN.
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at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
For information regarding Intersil Corporation and its products, see
in the quality certifications found at
17
For additional products, see
ISL8204M, ISL8206M
www.intersil.com/product_tree
Reflow Parameters
Due to the low mount height of the QFN, "No Clean" Type 3
solder paste per ANSI/J-STD-005 is recommended.
Nitrogen purge is also recommended during reflow. A
system board reflow profile depends on the thermal mass
of the entire populated board, so it is not practical to define
a specific soldering profile just for the QFN. The profile
given in Figure 30 is provided as a guideline, to be
customized for varying manufacturing practices and
applications.
www.intersil.com/design/quality
300
250
200
150
100
50
0
FIGURE 30. TYPICAL REFLOW PROFILE
0
SLOW RAMP (3°C/s MAX)
AND SOAK FROM +100°C
TO +180°C FOR 90s~120s
PEAK TEMPERATURE +230°C~+245°C;
TYPICALLY 60s-70s ABOVE +220°C
KEEP LESS THAN 30s WITHIN 5°C OF PEAK TEMP.
RAMP RATE ≤1.5°C FROM +70°C TO +90°C
100
150
www.intersil.com
DURATION (s)
200
250
December 16, 2010
300
FN6999.2
350