NUMICRO-SDK Nuvoton Technology Corporation of America, NUMICRO-SDK Datasheet
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... The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. ...
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... PARTS INFORMATION LIST AND PIN CONFIGURATION .................................................... 30 3.1 NuMicro™ NUC100 Products Selection Guide ............................................................. 30 3.1.1 NuMicro™ NUC100 Medium Density Advance Line Selection Guide .............................30 3.1.2 NuMicro™ NUC100 Low Density Advance Line Selection Guide ...................................30 3.2 NuMicro™ NUC120 Products Selection Guide ............................................................. 31 3.2.1 NuMicro™ ...
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... NuMicro™ NUC100 Series Technical Reference Manual 5.2.2 System Reset ...............................................................................................................113 5.2.3 System Power Distribution ...........................................................................................114 5.2.4 System Memory Map....................................................................................................116 5.2.5 System Manager Control Registers..............................................................................118 5.2.6 System Timer (SysTick) ...............................................................................................154 5.2.7 Nested Vectored Interrupt Controller (NVIC) ................................................................159 5.2.8 System Control Register...............................................................................................183 5 ...
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... NuMicro™ NUC100 Series Technical Reference Manual 5.8.2 Features .......................................................................................................................322 5.8.3 Block Diagram ..............................................................................................................323 5.8.4 Function Description.....................................................................................................324 5.8.5 Register Map ................................................................................................................326 5.8.6 Register Description .....................................................................................................327 5.9 Serial Peripheral Interface (SPI) ................................................................................. 341 5.9.1 Overview ......................................................................................................................341 5.9.2 Features .......................................................................................................................341 5.9.3 Block Diagram ..............................................................................................................342 5 ...
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... NuMicro™ NUC100 Series Technical Reference Manual 5.14.4 Functional Description ................................................................................................455 5.14.5 Register Map ..............................................................................................................460 5.14.6 Register Description ...................................................................................................461 Controller (I S)....................................................................................................... 468 5.15.1 Overview ....................................................................................................................468 5.15.2 Features .....................................................................................................................468 5.15.3 Block Diagram ............................................................................................................469 5.15.4 Functional Description ................................................................................................470 5.15.5 Register Map ..............................................................................................................472 5 ...
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... NuMicro™ NUC100 Series Technical Reference Manual 6.7 User Configuration...................................................................................................... 559 6.8 In System Program (ISP)............................................................................................ 562 6.8.1 ISP Procedure ..............................................................................................................562 6.9 Flash Control Register Map ........................................................................................ 565 6.10 Flash Control Register Description ............................................................................. 566 7 ELECTRICAL CHARACTERISTICS....................................................................................... 574 7.1 Absolute Maximum Ratings ........................................................................................ 574 7.2 DC Electrical Characteristics ...
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... Figure 3-8 NuMicro™ NUC130 Medium Density LQFP 100-pin Pin Diagram ............................... 41 Figure 3-9 NuMicro™ NUC130 Medium Density LQFP 64-pin Pin Diagram ................................. 42 Figure 3-10 NuMicro™ NUC130 Medium Density LQFP 48-pin Pin Diagram ............................... 43 Figure 3-11 NuMicro™ NUC140 Medium Density LQFP 100-pin Pin Diagram ............................. 44 Figure 3-12 NuMicro™ ...
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... NuMicro™ NUC100 Series Technical Reference Manual Figure 5-6 SysTick Clock Control Block Diagram ........................................................................ 192 Figure 5-7 Clock Source of Frequency Divider ............................................................................ 194 Figure 5-8 Block Diagram of Frequency Divider .......................................................................... 194 Figure 5-9 USB Block Diagram .................................................................................................... 216 Figure 5-10 Wakeup Interrupt Operation Flow............................................................................ 218 Figure 5-11 Endpoint SRAM Structure ...
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... NuMicro™ NUC100 Series Technical Reference Manual Figure 5-43 PWM Controller Output Duty Ratio........................................................................... 291 Figure 5-44 Paired-PWM Output with Dead Zone Generation Operation ................................... 291 Figure 5-45 Capture Operation Timing ........................................................................................ 292 Figure 5-46 PWM Group A PWM-Timer Interrupt Architecture Diagram..................................... 293 Figure 5-47 PWM Group B PWM-Timer Interrupt Architecture Diagram..................................... 293 Figure 5-48 RTC Block Diagram ...
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... NuMicro™ NUC100 Series Technical Reference Manual Figure 5-80 Format of ACK FIELD............................................................................................... 426 Figure 5-81 Format of REMOTE FRAME .................................................................................... 427 Figure 5-82 Format of ERROR FRAME....................................................................................... 427 Figure 5-83 PS/2 Device Block Diagram ..................................................................................... 454 Figure 5-84 Data Format of Device-to-Host................................................................................. 456 Figure 5-85 Data Format of Host-to-Device................................................................................. 456 Figure 5-86 PS/2 Bit Data Format ...
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... NuMicro™ NUC100 Series Technical Reference Manual Figure 6-3 Low Density Flash Memory Organization................................................................... 555 Figure 6-4 Low Density Flash Memory Organization................................................................... 556 Figure 6-5 Medium Density Flash Memory Structure .................................................................. 557 Figure 6-6 Low Density Flash Memory Structure......................................................................... 558 Figure 7-1 Typical Crystal Application Circuit .............................................................................. 589 ...
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... NuMicro™ NUC100 Series Technical Reference Manual Tables Table 1-1 Connectivity Supported Table........................................................................................ 13 Table 5-1 Address Space Assignments for On-Chip Controllers................................................. 117 Table 5-2 Exception Model .......................................................................................................... 160 Table 5-3 System Interrupt Map................................................................................................... 161 Table 5-4 Vector Table Format .................................................................................................... 162 Table 5-5 Power Down Mode Control Table................................................................................ 198 Table 5-6 Byte Order and Byte Suspend Conditions ...
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... NuMicro™ NUC100 Series includes NUC100, NUC120, NUC130 and NUC140 product line. The NuMicro™ NUC100 Advanced Line embeds Cortex™-M0 core running MHz with 32K/64K/128K-byte embedded flash, 4K/8K/16K-byte embedded SRAM, and 4K-byte loader ROM for the ISP. It also equips with plenty of peripheral devices, such as Timers, Watchdog Timer, RTC, PDMA, UART, SPI/MICROWIRE, I Analog Comparator, Low Voltage Reset Controller and Brown-out Detector ...
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... NuMicro™ NUC100 Series Technical Reference Manual 2 FEATURES The equipped features are dependent on the product line and their sub products. 2.1 NuMicro™ NUC100 Features – Advanced Line • Core ® ARM Cortex™-M0 core runs MHz – One 24-bit system timer – ...
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... NuMicro™ NUC100 Series Technical Reference Manual • Timer Support 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit pre-scale counter – Independent clock source for each timer – Provides one-shot, periodic, toggle and auto-reload counting operation modes – • Watch Dog Timer Multiple clock sources – ...
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... NuMicro™ NUC100 Series Technical Reference Manual 2 • two sets of I2C device – Master/Slave up to 1Mbit/s – Bidirectional data transfer between masters and slaves – Multi-master bus (no central master) – Arbitration between simultaneously transmitting masters without corruption of serial – data on the bus Serial clock synchronization allows devices with different bit rates to communicate via – ...
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... NuMicro™ NUC100 Series Technical Reference Manual Support Brownout Interrupt and Reset option – • Low Voltage Reset Threshold voltage levels: 2.0V – • Operating Temperature: -40℃~85℃ • Packages: All Green package (RoHS) – LQFP 100-pin / 64-pin / 48-pin (100-pin for Medium Density Only) – ...
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... NuMicro™ NUC100 Series Technical Reference Manual 2.2 NuMicro™ NUC120 Features – USB Line • Core ® ARM Cortex™-M0 core runs MHz – One 24-bit system timer – Supports low power sleep-mode – Single-cycle 32-bit hardware multiplier – NVIC for the 32 interrupt inputs, each with 4-levels of priority – ...
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... NuMicro™ NUC100 Series Technical Reference Manual • Watch Dog Timer Multiple clock sources – 8 selectable time out period from 6ms ~ 3.0sec (depends on clock source) – WDT can wake up from power down or sleep mode – Interrupt or reset selectable on watchdog time-out – ...
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... NuMicro™ NUC100 Series Technical Reference Manual 2 • two sets device – Master/Slave up to 1Mbit/s – Bidirectional data transfer between masters and slaves – Multi-master bus (no central master) – Arbitration between simultaneously transmitting masters without corruption of serial – data on the bus Serial clock synchronization allows devices with different bit rates to communicate via – ...
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... NuMicro™ NUC100 Series Technical Reference Manual • Analog Comparator Up to two analog comparator – External input or internal bandgap voltage selectable at negative node – Interrupt when compare result change – Power down wake up – • One built-in temperature sensor with 1℃ resolution • ...
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... NuMicro™ NUC100 Series Technical Reference Manual 2.3 NuMicro™ NUC130 Features – Automotive Line • Core ® ARM Cortex™-M0 core runs MHz – One 24-bit system timer – Supports low power sleep-mode – Single-cycle 32-bit hardware multiplier – NVIC for the 32 interrupt inputs, each with 4-levels of priority – ...
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... NuMicro™ NUC100 Series Technical Reference Manual • Watch Dog Timer Multiple clock sources – 8 selectable time out period from 6ms ~ 3.0sec (depends on clock source) – WDT can wake up from power down or sleep mode – Interrupt or reset selectable on watchdog time-out – ...
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... NuMicro™ NUC100 Series Technical Reference Manual 2 • two sets device – Master/Slave up to 1Mbit/s – Bidirectional data transfer between masters and slaves – Multi-master bus (no central master) – Arbitration between simultaneously transmitting masters without corruption of serial – data on the bus Serial clock synchronization allows devices with different bit rates to communicate via – ...
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... NuMicro™ NUC100 Series Technical Reference Manual Threshold voltage detection – Conversion start by software programming or external input – Support PDMA Mode – • Analog Comparator Up to two analog comparator – External input or internal bandgap voltage selectable at negative node – Interrupt when compare result change – ...
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... NuMicro™ NUC100 Series Technical Reference Manual 2.4 NuMicro™ NUC140 Features – Connectivity Line • Core ® ARM Cortex™-M0 core runs MHz – One 24-bit system timer – Supports low power sleep-mode – Single-cycle 32-bit hardware multiplier – NVIC for the 32 interrupt inputs, each with 4-levels of priority – ...
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... NuMicro™ NUC100 Series Technical Reference Manual • Watch Dog Timer Multiple clock sources – 8 selectable time out period from 6ms ~ 3.0sec (depends on clock source) – WDT can wake up from power down or sleep mode – Interrupt or reset selectable on watchdog time-out – ...
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... NuMicro™ NUC100 Series Technical Reference Manual 2 • two sets device – Master/Slave up to 1Mbit/s – Bidirectional data transfer between masters and slaves – Multi-master bus (no central master) – Arbitration between simultaneously transmitting masters without corruption of serial – data on the bus Serial clock synchronization allows devices with different bit rates to communicate via – ...
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... NuMicro™ NUC100 Series Technical Reference Manual Accessible space: 64KB in 8-bit mode or 128KB in 16-bit mode – Support 8bit/16bit data width – Support byte write in 16bit data width mode – • ADC 12-bit SAR ADC with 600K SPS – 8-ch single-end input or 4-ch differential input – ...
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... 4x32-bit NUC100RD3AN 4x32-bit NUC100RE3AN 128 Definable 4x32-bit NUC100VD2AN 4x32-bit NUC100VD3AN 4x32-bit NUC100VE3AN 128 Definable 4x32-bit 3.1.2 NuMicro™ NUC100 Low Density Advance Line Selection Guide ISP Data Part number APROM RAM Loader I/O Flash ROM NUC100LC1BN 4x32-bit NUC100LD1BN 4x32-bit NUC100LD2BN 64 KB ...
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... 4x32-bit NUC120RD3AN 4x32-bit NUC120RE3AN 128 Definable 4x32-bit NUC120VD2AN 4x32-bit NUC120VD3AN 4x32-bit NUC120VE3AN 128 Definable 4x32-bit 3.2.2 NuMicro™ NUC120 Low Density USB Line Selection Guide ISP Data Part number APROM RAM Loader I/O Flash ROM NUC120LC1BN 4x32-bit NUC120LD1BN 4x32-bit NUC120LD2BN 64 KB ...
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... NUC130RD3AN 4x32-bit NUC130RE3AN 128 Definable 4x32-bit NUC130VD2AN 4x32-bit NUC130VD3AN 4x32-bit NUC130VE3AN 128 Definable 4x32-bit 3.3.2 NuMicro™ NUC130 Low Density Automotive Line Selection Guide ISP Data Part number APROM RAM Loader I/O Flash ROM NUC130LC1BN 4x32-bit NUC130LD2BN 4x32-bit NUC130RC1BN 32 KB ...
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... NUC140RD3AN 4x32-bit NUC140RE3AN 128 Definable 4x32-bit NUC140VD2AN 4x32-bit NUC140VD3AN 4x32-bit NUC140VE3AN 128 Definable 4x32-bit 3.4.2 NuMicro™ NUC140 Low Density Connectivity Line Selection Guide ISP Data Part number APROM RAM Loader I/O Flash ROM NUC140LC1BN 4x32-bit NUC140LD2BN 4x32-bit NUC140RC1BN 32 KB ...
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... Cortex-M0 5/7: ARM7 9: ARM9 Function 0: Advance Line 2: USB Line 3: Automotive Line 4: Connectivity Line Package Type Y: QFN 36 L: LQFP 48 R: LQFP 64 V: LQFP 100 Figure 3-1 NuMicro™ NUC100 Series selection code - Temperature N: -40 ~ +85 E: -40 ~ +105 C: -40 ~ +125 Reserve RAM Size 1: 4K ...
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... CPP1/PC.14 90 INT1/PB.15 91 XT1_Out 92 XT1_In 93 /RESET 94 VSS 95 VDD 96 PS2DAT 97 PS2CLK 98 PVSS 99 STADC/TM0/PB.8 100 Figure 3-2 NuMicro™ NUC100 Medium Density LQFP 100-pin Pin Diagram NUC100 Medium Density LQFP 100-pin Publication Release Date: Oct 22, 2010 - PB.9/SPISS11/TM1 49 PB.10/SPISS01/TM2 48 PB.11/TM3/PWM4 47 PE.5/PWM5 46 PE.6 45 PC.0/SPISS00/I2SLRCLK 44 PC.1/SPICLK0/I2SBCLK 43 PC.2/MISO00/I2SDI 42 PC ...
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... CPP0/PC.6 54 CPN1/PC.15 55 CPP1/PC.14 56 INT1/PB.15 57 XT1_Out 58 XT1_In 59 /RESET 60 VSS 61 VDD 62 PVSS 63 STADC/TM0/PB.8 64 Figure 3-3 NuMicro™ NUC100 Medium Density LQFP 64-pin Pin Diagram NUC100 Medium Density LQFP 64-pin Publication Release Date: Dec. 22, 2010 - PB.9/TM1 31 PB.10/TM2 30 PB.11/TM3/PWM4 29 PE.5/PWM5 28 PC.0/SPISS00/I2SLRCLK 27 PC.1/SPICLK0/I2SBCLK 26 PC.2/MISO00/I2SDI 25 PC.3/MOSI00/I2SDO 24 PD.15/TX2 23 PD ...
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... NuMicro™ NUC100 Series Technical Reference Manual ™ 3.5.1.3 NuMicro NUC100 LQFP 48 pin Figure 3-4 NuMicro™ NUC100 Medium Density LQFP 48-pin Pin Diagram Publication Release Date: Oct 22, 2010 - 37 - Revision V1.06 ...
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... NuMicro™ NUC100 Series Technical Reference Manual ™ 3.5.1.4 NuMicro NUC120 LQFP 100 pin Figure 3-5 NuMicro™ NUC120 Medium Density LQFP 100-pin Pin Diagram Publication Release Date: Dec. 22, 2010 - 38 - Revision V1.06 ...
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... CPP0/PC.6 54 CPN1/PC.15 55 CPP1/PC.14 56 INT1/PB.15 57 XT1_Out 58 XT1_In 59 /RESET 60 VSS 61 VDD 62 PVSS 63 STADC/TM0/PB.8 64 Figure 3-6 NuMicro™ NUC120 Medium Density LQFP 64-pin Pin Diagram NUC120 Medium Density LQFP 64-pin Publication Release Date: Oct 22, 2010 - PB.9/TM1 31 PB.10/TM2 30 PB.11/TM3/PWM4 29 PE.5/PWM5 28 PC.0/SPISS00/I2SLRCLK 27 PC.1/SPICLK0/I2SBCLK 26 PC.2/MISO00/I2SDI 25 PC.3/MOSI00/I2SDO 24 PB.3/CTS0 23 PB ...
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... NuMicro™ NUC100 Series Technical Reference Manual ™ 3.5.1.6 NuMicro NUC120 LQFP 48 pin Figure 3-7 NuMicro™ NUC120 Medium Density LQFP 48-pin Pin Diagram Publication Release Date: Dec. 22, 2010 - 40 - Revision V1.06 ...
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... NuMicro™ NUC100 Series Technical Reference Manual ™ 3.5.1.7 NuMicro NUC130 LQFP 100 pin Figure 3-8 NuMicro™ NUC130 Medium Density LQFP 100-pin Pin Diagram Publication Release Date: Oct 22, 2010 - 41 - Revision V1.06 ...
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... CPP0/PC.6 54 CPN1/PC.15 55 CPP1/PC.14 56 INT1/PB.15 57 XT1_Out 58 XT1_In 59 /RESET 60 VSS 61 VDD 62 PVSS 63 STADC/TM0/PB.8 64 Figure 3-9 NuMicro™ NUC130 Medium Density LQFP 64-pin Pin Diagram NUC130 Medium Density LQFP 64-pin Publication Release Date: Dec. 22, 2010 - PB.9/TM1 31 PB.10/TM2 30 PB.11/TM3/PWM4 29 PE.5/PWM5 28 PC.0/SPISS00/I2SLRCLK 27 PC.1/SPICLK0/I2SBCLK 26 PC.2/MISO00/I2SDI 25 PC.3/MOSI00/I2SDO 24 PD.15/TX2 23 PD ...
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... NuMicro™ NUC100 Series Technical Reference Manual ™ 3.5.1.9 NuMicro NUC130 LQFP 48 pin Figure 3-10 NuMicro™ NUC130 Medium Density LQFP 48-pin Pin Diagram Publication Release Date: Oct 22, 2010 - 43 - Revision V1.06 ...
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... NuMicro™ NUC100 Series Technical Reference Manual ™ 3.5.1.10 NuMicro NUC140 LQFP 100 pin Figure 3-11 NuMicro™ NUC140 Medium Density LQFP 100-pin Pin Diagram Publication Release Date: Dec. 22, 2010 - 44 - Revision V1.06 ...
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... NuMicro™ NUC100 Series Technical Reference Manual ™ 3.5.1.11 NuMicro NUC140 LQFP 64 pin Figure 3-12 NuMicro™ NUC140 Medium Density LQFP 64-pin Pin Diagram Publication Release Date: Oct 22, 2010 - 45 - Revision V1.06 ...
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... NuMicro™ NUC100 Series Technical Reference Manual ™ 3.5.1.12 NuMicro NUC140 LQFP 48 pin Figure 3-13 NuMicro™ NUC140 Medium Density LQFP 48-pin Pin Diagram Publication Release Date: Dec. 22, 2010 - 46 - Revision V1.06 ...
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... NuMicro™ NUC100 Series Technical Reference Manual 3.5.2 NuMicro™ NUC100/120/130/140 Low Density Pin Diagram ™ 3.5.2.1 NuMicro NUC100 LQFP 64 pin Figure 3-14 NuMicro™ NUC100 Low Density LQFP 64-pin Pin Diagram Publication Release Date: Oct 22, 2010 - 47 - Revision V1.06 ...
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... NuMicro™ NUC100 Series Technical Reference Manual ™ 3.5.2.2 NuMicro NUC100 LQFP 48 pin Figure 3-15 NuMicro™ NUC100 Low Density LQFP 48-pin Pin Diagram Publication Release Date: Dec. 22, 2010 - 48 - Revision V1.06 ...
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... NuMicro™ NUC100 Series Technical Reference Manual ™ 3.5.2.3 NuMicro NUC120 LQFP 64 pin Figure 3-16 NuMicro™ NUC120 Low Density LQFP 64-pin Pin Diagram Publication Release Date: Oct 22, 2010 - 49 - Revision V1.06 ...
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... ADC5/PA.5 37 ADC6/PA.6 38 ADC7/PA.7 39 AVDD 40 CPN0/PC.7 41 CPP0/PC.6 42 INT1/PB.15 43 XT1_Out 44 XT1_In 45 /RESET 46 PVSS 47 STADC/TM0/PB.8 48 Figure 3-17 NuMicro™ NUC120 Low Density LQFP 48-pin Pin Diagram NUC120 20 19 Low Density 18 LQFP 48-pin Publication Release Date: Dec. 22, 2010 - 50 - PC.0/SPISS00/I2SLRCLK PC.1/SPICLK0/I2SBCLK PC.2/MISO00/I2SDI PC.3/MOSI00/I2SDO PB.3/CTS0 PB.2/RTS0 PB.1/TX0 PB ...
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... NuMicro™ NUC100 Series Technical Reference Manual ™ 3.5.2.5 NuMicro NUC130 LQFP 64 pin Figure 3-18 NuMicro™ NUC130 Low Density LQFP 64-pin Pin Diagram Publication Release Date: Oct 22, 2010 - 51 - Revision V1.06 ...
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... NuMicro™ NUC100 Series Technical Reference Manual ™ 3.5.2.6 NuMicro NUC130 LQFP 48 pin Figure 3-19 NuMicro™ NUC130 Low Density LQFP 48-pin Pin Diagram Publication Release Date: Dec. 22, 2010 - 52 - Revision V1.06 ...
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... NuMicro™ NUC100 Series Technical Reference Manual ™ 3.5.2.7 NuMicro NUC140 LQFP 64 pin Figure 3-20 NuMicro™ NUC140 Low Density LQFP 64-pin Pin Diagram Publication Release Date: Oct 22, 2010 - 53 - Revision V1.06 ...
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... NuMicro™ NUC100 Series Technical Reference Manual ™ 3.5.2.8 NuMicro NUC140 LQFP 48 pin Figure 3-21 NuMicro™ NUC140 Low Density LQFP 48-pin Pin Diagram Publication Release Date: Dec. 22, 2010 - 54 - Revision V1.06 ...
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... NuMicro™ NUC100 Series Technical Reference Manual 3.6 Pin Description 3.6.1 NuMicro™ NUC100/NUC120/NUC130/NUC140 Medium Density Pin Description ™ 3.6.1.1 NuMicro NUC100 Medium Density Pin Description Pin No. Pin Name Pin Type LQFP LQFP LQFP 100 PE.15 2 PE.14 3 PE.13 PB. /INT0 SPISS31 PB.13 ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP LQFP 100 64 48 MISO30 I PD.11 I/O 16 MOSI30 O PD.12 I/O 17 MISO31 I PD.13 I/O 18 MOSI31 O PB.4 I RXD1 I PB.5 I TXD1 O PB.6 I RTS1 PB.7 I CTS1 LDO VDD VSS P 26 PE.12 I ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP LQFP 100 64 48 PB.3 I CTS0 36 21 PD.6 I PD.7 I/O PD.14 I RXD2 I PD.15 I TXD2 O PC.5 I/O 40 MOSI01 O PC.4 I/O 41 MISO01 I PC.3 I MOSI00 O I2SDO O PC.2 I MISO00 I I2SDI I PC.1 I/O ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP LQFP 100 64 48 PB.10 I TM2 O SPISS01 I/O PB.9 I TM1 O SPISS11 I/O 51 PE.4 I/O 52 PE.3 I/O 53 PE.2 I/O PE.1 I/O 54 PWM7 O PE.0 I/O 55 PWM6 O PC.13 I/O 56 MOSI11 O PC.12 ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP LQFP 100 64 48 PA.13 I PWM1 O PA.12 I PWM0 ICE_DAT I ICE_CK I 68 VDD P 69 VSS AVSS AP PA.0 I ADC0 AI PA.1 I ADC1 AI PA.2 I ADC2 AI PA.3 I ADC3 AI PA.4 I ADC4 AI PA.5 I ADC5 AI PA.6 ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP LQFP 100 64 48 PD.1 I/O 82 SPICLK2 I/O PD.2 I/O 83 MISO20 I PD.3 I/O 84 MOSI20 O PD.4 I/O 85 MISO21 I PD.5 I/O 86 MOSI21 O PC.7 I CPN0 I PC.6 I CPP0 I PC.15 I CPN1 I PC.14 I/O ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP LQFP 100 64 48 STADC TM0 O Note: Pin Type I=Digital Input, O=Digital Output; AI=Analog Input; P=Power Pin; AP=Analog Power Description STADC: ADC external trigger input. I TM0: Timer0 external counter input ...
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... NuMicro™ NUC100 Series Technical Reference Manual ™ 3.6.1.2 NuMicro NUC120 Medium Density Pin Description Pin No. Pin Name Pin Type LQFP LQFP LQFP 100 PE.15 2 PE.14 3 PE.13 PB. /INT0 SPISS31 PB. CPO1 PB. CPO0 CLKO X32O X32I PA. I2C1SCL PA. I2C1SDA PA I2C0SCL PA I2C0SDA PD.8 13 SPISS30 PD.9 ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP LQFP 100 64 48 MOSI30 O PD.12 I/O 17 MISO31 I PD.13 I/O 18 MOSI31 O PB.4 I RXD1 I PB.5 I TXD1 O PB.6 I RTS1 PB.7 I CTS1 LDO VDD VSS P 26 PE.8 I/O 27 PE.7 I VBUS USB ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP LQFP 100 64 48 CTS0 36 PD.6 I/O 37 PD.7 I/O PD.14 I/O 38 RXD2 I PD.15 I/O 39 TXD2 O PC.5 I/O 40 MOSI01 O PC.4 I/O 41 MISO01 I PC.3 I MOSI00 O I2SDO O PC.2 I MISO00 I I2SDI I PC.1 ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP LQFP 100 64 48 TM2 O SPISS01 I/O PB.9 I TM1 O SPISS11 I/O 51 PE.4 I/O 52 PE.3 I/O 53 PE.2 I/O PE.1 I/O 54 PWM7 O PE.0 I/O 55 PWM6 O PC.13 I/O 56 MOSI11 O PC.12 I/O ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP LQFP 100 64 48 PWM1 O PA.12 I PWM0 ICE_DAT I ICE_CK I 68 VDD P 69 VSS AVSS AP PA.0 I ADC0 AI PA.1 I ADC1 AI PA.2 I ADC2 AI PA.3 I ADC3 AI PA.4 I ADC4 AI PA.5 I ADC5 AI PA.6 I/O ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP LQFP 100 64 48 SPICLK2 I/O PD.2 I/O 83 MISO20 I PD.3 I/O 84 MOSI20 O PD.4 I/O 85 MISO21 I PD.5 I/O 86 MOSI21 O PC.7 I CPN0 I PC.6 I CPP0 I PC.15 I CPN1 I PC.14 I CPP1 I PB.15 I/O ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP LQFP 100 64 48 TM0 O Note: Pin Type I=Digital Input, O=Digital Output; AI=Analog Input; P=Power Pin; AP=Analog Power Description TM0: Timer0 external counter input Publication Release Date: Dec. 22, 2010 - 68 - Revision V1 ...
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... NuMicro™ NUC100 Series Technical Reference Manual ™ 3.6.1.3 NuMicro NUC130 Medium Density Pin Description Pin No. Pin Name Pin Type LQFP LQFP LQFP 100 PE.15 2 PE.14 3 PE.13 PB. /INT0 SPISS31 PB. CPO1 PB. CPO0 CLKO X32O X32I PA. I2C1SCL PA. I2C1SDA PA I2C0SCL PA I2C0SDA PD.8 13 SPISS30 PD.9 ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP LQFP 100 64 48 MOSI30 O PD.12 I/O 17 MISO31 I PD.13 I/O 18 MOSI31 O PB.4 I RXD1 I PB.5 I TXD1 O PB.6 I RTS1 PB.7 I CTS1 LDO VDD VSS P 26 PE.12 I/O 27 PE.11 I/O 28 PE.10 ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP LQFP 100 64 48 PD.6 I CANRX0 I PD.7 I CANTX0 PD.14 I/O 38 RXD2 PD.15 I/O 39 TXD2 O PC.5 I/O 40 MOSI01 O PC.4 I/O 41 MISO01 I PC.3 I MOSI00 O I2SDO O PC.2 I MISO00 I I2SDI I PC.1 I/O ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP LQFP 100 64 48 PWM4 O PB.10 I TM2 O SPISS01 I/O PB.9 I TM1 O SPISS11 I/O 51 PE.4 I/O 52 PE.3 I/O 53 PE.2 I/O PE.1 I/O 54 PWM7 O PE.0 I/O 55 PWM6 O PC.13 I/O 56 MOSI11 O PC ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP LQFP 100 64 48 PWM2 O PA.13 I PWM1 O PA.12 I PWM0 ICE_DAT I ICE_CK I 68 VDD P 69 VSS AVSS AP PA.0 I ADC0 AI PA.1 I ADC1 AI PA.2 I ADC2 AI PA.3 I ADC3 AI PA.4 I ADC4 AI PA.5 I/O ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP LQFP 100 64 48 SPISS20 I/O PD.1 I/O 82 SPICLK2 I/O PD.2 I/O 83 MISO20 I PD.3 I/O 84 MOSI20 O PD.4 I/O 85 MISO21 I PD.5 I/O 86 MOSI21 O PC.7 I CPN0 I PC.6 I CPP0 I PC.15 I/O ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP LQFP 100 64 48 PB.8 I/O 100 64 48 STADC TM0 O Note: Pin Type I=Digital Input, O=Digital Output; AI=Analog Input; P=Power Pin; AP=Analog Power Description General purpose input/output digital pin STADC: ADC external trigger input ...
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... NuMicro™ NUC100 Series Technical Reference Manual ™ 3.6.1.4 NuMicro NUC140 Medium Density Pin Description Pin No. Pin Name Pin Type LQFP LQFP LQFP 100 PE.15 2 PE.14 3 PE.13 PB. /INT0 SPISS31 PB. CPO1 PB. CPO0 CLKO X32O X32I PA. I2C1SCL PA. I2C1SDA PA I2C0SCL PA I2C0SDA PD.8 13 SPISS30 PD.9 ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP LQFP 100 64 48 MOSI30 O PD.12 I/O 17 MISO31 I PD.13 I/O 18 MOSI31 O PB.4 I RXD1 I PB.5 I TXD1 O PB.6 I RTS1 PB.7 I CTS1 LDO VDD VSS P 26 PE.8 I/O 27 PE.7 I VBUS USB ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP LQFP 100 64 48 CTS0 PD.6 I CANRX0 I PD.7 I CANTX0 O PD.14 I RXD2 I PD.15 I TXD2 O PC.5 I/O 40 MOSI01 O PC.4 I/O 41 MISO01 I PC.3 I MOSI00 O I2SDO O PC.2 I MISO00 I I2SDI I PC.1 I/O SPICLK0 ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP LQFP 100 64 48 TM3 O PWM4 O PB.10 I/O 49 TM2 O SPISS01 I/O PB.9 I/O 50 TM1 O SPISS11 I/O 51 PE.4 I/O 52 PE.3 I/O 53 PE.2 I/O PE.1 I/O 54 PWM7 O PE.0 I/O 55 PWM6 O PC ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP LQFP 100 64 48 PA.14 I PWM2 O PA.13 I PWM1 O PA.12 I PWM0 ICE_DAT I ICE_CK I 68 VDD P 69 VSS AVSS AP PA.0 I ADC0 AI PA.1 I ADC1 AI PA.2 I ADC2 AI PA.3 I ADC3 AI PA.4 I ADC4 AI PA.5 ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP LQFP 100 64 48 PD.0 I/O 81 SPISS20 I/O PD.1 I/O 82 SPICLK2 I/O PD.2 I/O 83 MISO20 I PD.3 I/O 84 MOSI20 O PD.4 I/O 85 MISO21 I PD.5 I/O 86 MOSI21 O PC.7 I CPN0 I PC.6 I/O ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP LQFP 100 PVSS P PB.8 I/O 100 64 48 STADC TM0 O Note: Pin Type I=Digital Input, O=Digital Output; AI=Analog Input; P=Power Pin; AP=Analog Power Description PLL Ground General purpose input/output digital pin STADC: ADC external trigger input ...
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... NuMicro™ NUC100 Series Technical Reference Manual 3.6.2 NuMicro™ NUC100/NUC120/NUC130/NUC140 Low Density Pin Description ™ 3.6.2.1 NuMicro NUC100 Low Density Pin Description Pin No. Pin Name Pin Type LQFP LQFP 64 48 PB.14 I/O 1 /INT0 I PB.13 I/O 2 CPO1 O AD1 I/O PB.12 I/O ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP 64 48 ALE O PB.7 I/O CTS1 13 nCS LDO VDD VSS P PB.0 I RXD0 I PB.1 I TXD0 O PB.2 I/O 15 RTS0 19 nWRL O PB.3 I/O 16 CTS0 20 nWRH O 21 PD.6 I/O 22 PD.7 I/O 23 PD.14 ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP 64 48 PC.1 I SPICLK0 I/O I2SBCLK I/O PC.0 I SPISS00 I/O I2SLRCLK I PE.5 I/O PB.11 I TM3 O PB.10 I TM2 O PB.9 I TM1 O PC.11 I/O 33 MOSI10 O PC.10 I/O 34 MISO10 I PC.9 I/O 35 SPICLK1 I/O PC ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP 64 48 AD14 I/O PA.12 I PWM0 O AD13 I ICE_DAT I ICE_CK AVSS AP PA.0 I ADC0 AI PA.1 I ADC1 AI AD12 I/O PA.2 I ADC2 AI AD11 I/O PA.3 I ADC3 AI AD10 I/O PA.4 I ADC4 AI AD9 I/O PA ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP AVDD AP PC.7 I CPN0 I AD5 I/O PC.6 I CPP0 I AD4 I/O PC.15 I/O 55 CPN1 I AD3 I/O PC.14 I/O 56 CPP1 I AD2 I/O PB.15 I /INT1 XT1_OUT XT1_IN /RESET I 61 VSS P 62 ...
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... NuMicro™ NUC100 Series Technical Reference Manual ™ 3.6.2.2 NuMicro NUC120 Low Density Pin Description Pin No. Pin Name Pin Type LQFP LQFP 64 48 PB.14 I/O 1 /INT0 I PB.13 I/O 2 CPO1 O AD1 I/O PB.12 I/O 1 CPO0 O 3 CLKO O AD0 I X32O X32I I PA.11 I/O ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP 64 48 PB.7 I/O CTS1 13 nCS LDO VDD VSS VBUS USB 18 14 VDD33 USB USB USB PB.0 I RXD0 I PB.1 I TXD0 O PB.2 I/O 19 RTS0 23 nWRL O PB.3 I/O 20 CTS0 24 nWRH O PC ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP 64 48 I2SBCLK I/O PC.0 I SPISS00 I/O I2SLRCLK I/O 29 PE.5 I/O PB.11 I/O 30 TM3 O PB.10 I/O 31 TM2 O PB.9 I/O 32 TM1 O PC.11 I/O 33 MOSI10 O PC.10 I/O 34 MISO10 I PC.9 I/O ...
Page 91
... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP 64 48 PWM0 O AD13 I ICE_DAT I ICE_CK AVSS AP PA.0 I ADC0 AI PA.1 I ADC1 AI AD12 I/O PA.2 I ADC2 AI AD11 I/O PA.3 I ADC3 AI AD10 I/O PA.4 I ADC4 AI AD9 I/O PA.5 I ADC5 AI AD8 I/O PA ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP 64 48 CPN0 I AD5 I/O PC.6 I CPP0 I AD4 I/O PC.15 I/O 55 CPN1 I AD3 I/O PC.14 I/O 56 CPP1 I AD2 I/O PB.15 I /INT1 XT1_OUT XT1_IN /RESET I 61 VSS P 62 VDD ...
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... NuMicro™ NUC100 Series Technical Reference Manual ™ 3.6.2.3 NuMicro NUC130 Low Density Pin Description Pin No. Pin Name Pin Type LQFP LQFP 64 48 PB.14 I/O 1 /INT0 I PB.13 I/O 2 CPO1 O AD1 I/O PB.12 I/O 1 CPO0 O 3 CLKO O AD0 I X32O X32I I PA.11 I/O ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP 64 48 PB.7 I/O CTS1 13 nCS LDO VDD VSS P PB.0 I RXD0 I PB.1 I TXD0 O PB.2 I/O 15 RTS0 19 nWRL O PB.3 I/O 16 CTS0 20 nWRH O PD.6 I CANRX0 I PD.7 I CANTX0 PD.14 I PD.15 I/O PC ...
Page 95
... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP 64 48 PC.1 I SPICLK0 I/O I2SBCLK I/O PC.0 I SPISS00 I/O I2SLRCLK I/O 29 PE.5 I/O PB.11 I/O 30 TM3 O PB.10 I/O 31 TM2 O PB.9 I/O 32 TM1 O PC.11 I/O 33 MOSI10 O PC.10 I/O ...
Page 96
... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP 64 48 PWM1 O AD14 I/O PA.12 I PWM0 O AD13 I ICE_DAT I ICE_CK AVSS AP PA.0 I ADC0 AI PA.1 I ADC1 AI AD12 I/O PA.2 I ADC2 AI AD11 I/O PA.3 I ADC3 AI AD10 I/O PA.4 I ADC4 AI AD9 I/O PA ...
Page 97
... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP 64 48 AD6 I AVDD AP PC.7 I CPN0 I AD5 I/O PC.6 I CPP0 I AD4 I/O PC.15 I/O 55 CPN1 I AD3 I/O PC.14 I/O 56 CPP1 I AD2 I/O PB.15 I /INT1 XT1_OUT XT1_IN /RESET I 61 ...
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... NuMicro™ NUC100 Series Technical Reference Manual ™ 3.6.2.4 NuMicro NUC140 Low Density Pin Description Pin No. Pin Name Pin Type LQFP LQFP 64 48 PB.14 I/O 1 /INT0 I PB.13 I/O 2 CPO1 O AD1 I/O PB.12 I/O 1 CPO0 O 3 CLKO O AD0 I X32O X32I I PA.11 I/O ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP 64 48 PB.7 I/O CTS1 13 nCS LDO VDD VSS VBUS USB 18 14 VDD33 USB USB USB PB.0 I RXD0 I PB.1 I TXD0 O PB.2 I/O RTS0 23 nWRL O PB.3 I/O CTS0 24 nWRH O PD ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP 64 48 MOSI00 O I2SDO O PC.2 I MISO00 I I2SDI I PC.1 I SPICLK0 I/O I2SBCLK I/O PC.0 I SPISS00 I/O I2SLRCLK I/O PC.11 I/O 33 MOSI10 O PC.10 I/O 34 MISO10 I PC.9 I/O 35 SPICLK1 I/O PC.8 ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP 64 48 PWM0 O AD13 I ICE_DAT I ICE_CK AVSS AP PA.0 I ADC0 AI PA.1 I ADC1 AI AD12 I/O PA.2 I ADC2 AI AD11 I/O PA.3 I ADC3 AI AD10 I/O PA.4 I ADC4 AI AD9 I/O PA.5 I ADC5 AI AD8 I/O PA ...
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... NuMicro™ NUC100 Series Technical Reference Manual Pin No. Pin Name Pin Type LQFP LQFP 64 48 CPN0 I AD5 I/O PC.6 I CPP0 I AD4 I/O PC.15 I/O 55 CPN1 I AD3 I/O PC.14 I/O 56 CPP1 I AD2 I/O PB.15 I /INT1 XT1_OUT XT1_IN /RESET I 61 VSS P 62 VDD ...
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... SRAM ISP 4KB 16KB PS2 SPI 2/3 I2C 1 -1M UART 1 -115K UART 2 -115K I2S Peripherals with PDMA Figure 4-1 NuMicro™ NUC100 Medium Density Block Diagram PDMA 50MHz GPIO CLK_CTL A,B,C,D,E RTC WDT SPI 0/1 Timer 0/1/ UART 0 -3M Timer 2/3 ...
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... SRAM ISP 4KB 16KB PS2 SPI 2/3 I2C 1 -1M UART 1 -115K UART 2 -115K I2S Peripherals with PDMA Figure 4-2 NuMicro™ NUC120 Medium Density Block Diagram PDMA 50MHz GPIO CLK_CTL A,B,C,D,E RTC WDT SPI 0/1 Timer 0/1/ UART 0 -3M Timer 2/3 ...
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... SRAM ISP 4KB 16KB PS2 SPI 2/3 I2C 1 -1M UART 1 -115K UART 2 -115K I2S Peripherals with PDMA Figure 4-3 NuMicro™ NUC130 Medium Density Block Diagram PDMA 50MHz GPIO CLK_CTL A,B,C,D,E RTC WDT SPI 0/1 Timer 0/1/ UART 0 -3M Timer 2/3 ...
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... SRAM ISP 4KB 16KB PS2 SPI 2/3 I2C 1 -1M UART 1 -115K UART 2 -115K I2S Peripherals with PDMA Figure 4-4 NuMicro™ NUC140 Medium Density Block Diagram PDMA 50MHz GPIO CLK_CTL A,B,C,D,E RTC WDT SPI 0/1 Timer 0/1/ UART 0 -3M Timer 2/3 ...
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... NuMicro™ NUC100 Series Technical Reference Manual 4.2 NuMicro™ NUC100/NUC120/NUC130/NUC140 Low Density Block Diagram 4.2.1 NuMicro™ NUC100 Low Density Block Diagram Figure 4-5 NuMicro™ NUC100 Low Density Block Diagram Publication Release Date: Oct 22, 2010 - 107 - Revision V1.06 ...
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... NuMicro™ NUC120 Low Density Block Diagram Cortex-M0 FLASH 64KB SRAM ISP 4KB 8KB I2C 1 -1M UART 1 -115K I2S Peripherals with PDMA Figure 4-6 NuMicro™ NUC120 Low Density Block Diagram PDMA 50MHz GPIO CLK_CTL A,B,C,D,E RTC WDT SPI 0/1 Timer 0/1/ UART 0 -3M ...
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... NuMicro™ NUC130 Low Density Block Diagram Cortex-M0 FLASH 64KB SRAM ISP 4KB 8KB I2C 1 -1M UART 1 -115K I2S Peripherals with PDMA Figure 4-7 NuMicro™ NUC130 Low Density Block Diagram PDMA 50MHz GPIO CLK_CTL A,B,C,D,E RTC WDT SPI 0/1 Timer 0/1/ UART 0 -3M ...
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... NuMicro™ NUC140 Low Density Block Diagram Cortex-M0 FLASH 64KB SRAM ISP 4KB 8KB I2C 1 -1M UART 1 -115K I2S Peripherals with PDMA Figure 4-8 NuMicro™ NUC140 Low Density Block Diagram PDMA 50MHz GPIO CLK_CTL A,B,C,D RTC WDT SPI 0/1 Timer 0/1/ UART 0 -3M ...
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... NuMicro™ NUC100 Series Technical Reference Manual 5 FUNCTIONAL DESCRIPTION ® 5.1 ARM Cortex™-M0 Core The Cortex™-M0 processor is a configurable, multistage, 32-bit RISC processor. It has an AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug functionality. The processor can execute Thumb code and is compatible with other Cortex-M profile processor ...
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... NuMicro™ NUC100 Series Technical Reference Manual NVIC that features: 32 external interrupt inputs, each with four levels of priority Dedicated Non-Maskable Interrupt (NMI) input. Support for both level-sensitive and pulse-sensitive interrupt lines Wake-up Interrupt Controller (WIC), providing ultra-low power sleep mode support. ...
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... NuMicro™ NUC100 Series Technical Reference Manual 5.2 System Manager 5.2.1 Overview System management includes these following sections: System Resets System Memory Map System management registers for Part Number ID, chip reset and on-chip controllers reset , multi-functional pin control System Timer (SysTick) ...
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... The outputs of internal voltage regulators, LDO and VDD33, require an external capacitor which should be located close to the corresponding pin. Figure 5-2 shows the power distribution of NuMicro™ NUC120/NUC140 and Figure 5-3 shows the power distribution of NuMicro™ NUC100/ NUC130 Figure 5-2 NuMicro™ NUC120/NUC140 Power Distribution Diagram Publication Release Date: Dec ...
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... Low Brown Voltage Out Reset Detector Temperature FLASH Seneor External 32.768 kHz PLL Crystal Figure 5-3 NuMicro™ NUC100/ NUC130 Power Distribution Diagram NUC100/ NUC130 Power Distribution Internal Digital Logic 22.1184 MHz & 10 kHz Oscillator 2.5V POR25 5V to 2.5V IO cell LDO ...
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... System Memory Map NuMicro™ NUC100 Series provides 4G-byte addressing space. The memory locations assigned to each on-chip controllers are shown in the following table. The detailed register definition, memory space, and programming detailed will be described in the following sections for each on- chip peripherals. NuMicro™ ...
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... NuMicro™ NUC100 Series Technical Reference Manual 0x4006_0000 – 0x4006_3FFF USBD_BA 0x400D_0000 – 0x400D_3FFF ACMP_BA 0x400E_0000 – 0x400E_FFFF ADC_BA APB2 Controllers Space (0x4010_0000 ~ 0x401F_FFFF) 0x4010_0000 – 0x4010_3FFF PS2_BA 0x4011_0000 – 0x4011_3FFF TMR23_BA 0x4012_0000 – 0x4012_3FFF I2C1_BA 0x4013_0000 – 0x4013_3FFF SPI2_BA 0x4013_4000 – 0x4013_7FFF SPI3_BA 0x4014_0000 – ...
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... NuMicro™ NUC100 Series Technical Reference Manual 5.2.5 System Manager Control Registers R: read only, W: write only, R/W: both read and write Register Offset R/W GCR_BA = 0x5000_0000 GCR_BA+0x00 R PDID GCR_BA+0x04 R/W RSTSRC GCR_BA+0x08 R/W IPRSTC1 GCR_BA+0x0C R/W IPRSTC2 GCR_BA+0x10 R/W CPR GCR_BA+0x18 ...
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... NuMicro™ NUC100 Series Technical Reference Manual Part Device ID Code Register (PDID) Register Offset R/W Description GCR_BA+0x00 R Part Device Identification Number Register PDID [1] Every part number has a unique default reset value Bits Descriptions Part Device Identification Number [31:0] PDID This register reflects device part number code. S/W can read this register to identify which device is used ...
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... NuMicro™ NUC100 Series Technical Reference Manual System Reset Source Register (RSTSRC) This register provides specific information for software to identify this chip’s reset source from last operation. Register Offset R/W Description GCR_BA+0x04 R/W System Reset Source Register RSTSRC RSTS_CPU Reserved ...
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... NuMicro™ NUC100 Series Technical Reference Manual Software can write 1 to clear this bit to zero. The RSTS_WDT flag is set by the “reset signal” from the watchdog timer to indicate the previous reset source The watchdog timer had issued the reset signal to reset the system. ...
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... NuMicro™ NUC100 Series Technical Reference Manual Peripheral Reset Control Register1 (IPRSTC1) Register Offset R/W Description GCR_BA+0x08 R/W IP Reset Control Register 1 IPRSTC1 Reserved Bits Descriptions [31:4] Reserved Reserved EBI Controller Reset (Low Density 64 pin package Only) (write-protection bit in NUC100/NUC120/NUC130/NUC140 Low Density 64-pin package) Set this bit to 1 will generate a reset signal to the EBI ...
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... NuMicro™ NUC100 Series Technical Reference Manual Setting this bit will reset the whole chip, including CPU kernel and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. The CHIP_RST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload ...
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... NuMicro™ NUC100 Series Technical Reference Manual Peripheral Reset Control Register2 (IPRSTC2) Setting these bits 1 will generate asynchronous reset signals to the corresponding IP controller. Users need to set these bits release corresponding IP controller from reset state Register Offset R/W Description GCR_BA+0x0C R/W Peripheral Controller Reset Control Register 2 ...
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... NuMicro™ NUC100 Series Technical Reference Manual 1 = PWM47 controller reset 0 = PWM47 controller normal operation PWM03 controller Reset [20 PWM03 controller reset PWM03_RST 0 = PWM03 controller normal operation [19] Reserved Reserved UART2 controller Reset (Medium Density Only) [18 UART2 controller reset UART2_RST 0 = UART2 controller normal operation ...
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... NuMicro™ NUC100 Series Technical Reference Manual 1 = Timer2 controller reset 0 = Timer2 controller normal operation Timer1 controller Reset [ Timer1 controller reset TMR1_RST 0 = Timer1 controller normal operation Timer0 controller Reset [ Timer0 controller reset TMR0_RST 0 = Timer0 controller normal operation GPIO controller Reset [ GPIO controller reset ...
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... NuMicro™ NUC100 Series Technical Reference Manual High Performance Mode Register (CPR) This register is used to control CHIP performance (Low Density Only) Register Offset R/W Description GCR_BA+0x10 R/W High Performance Mode Register CPR Bits Descriptions [31:1] Reserved Reversed High Performance Enable (write-protection bit) This bit is used to control chip operation performance ...
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... NuMicro™ NUC100 Series Technical Reference Manual Brown-Out Detector Control Register (BODCR) Partial of the BODCR control registers values are initiated by the flash configuration and partial bits are write-protected bit. Programming write-protected bits needs to write “59h”, “16h”, “88h” to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at ...
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... NuMicro™ NUC100 Series Technical Reference Manual REGWRPROT at address GCR_BA+0x100. Brown Out Detector Interrupt Flag 1 = When Brown Out Detector detects the VDD is dropped down through the voltage of BOD_VL setting or the VDD is raised up through the voltage of BOD_VL setting, this bit is set to 1 and the brown out interrupt is requested if brown out interrupt is enabled. ...
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... NuMicro™ NUC100 Series Technical Reference Manual Temperature Sensor Control Register (TEMPCR) Register Offset R/W Description GCR_BA+0x1C R/W Temperature Sensor Control Register TEMPCR Bits Descriptions [31:1] Reserved Reserved Temperature sensor Enable This bit is used to enable/disable temperature sensor function Enabled temperature sensor function ...
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... NuMicro™ NUC100 Series Technical Reference Manual Power-On-Reset Control Register (PORCR) Register Offset R/W Description GCR_BA+0x24 R/W Power-On-Reset Controller Register PORCR Bits Descriptions [31:16] Reserved Reserved The register is used for the Power-On-Reset enable control (write-protection bits) When power on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again ...
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... NuMicro™ NUC100 Series Technical Reference Manual Multiple Function Pin GPIOA Control Register (GPA_MFP) Register Offset R/W Description GCR_BA+0x30 R/W GPIOA Multiple Function and Input Type Control Register GPA_MFP Bits Descriptions 1 = Enable GPIOA[15:0] I/O input Schmitt Trigger function [31:16] GPA_TYPEn 0 = Disable GPIOA[15:0] I/O input Schmitt Trigger function PA ...
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... NuMicro™ NUC100 Series Technical Reference Manual 0 1 PA.12 Pin Function Selection The pin function depends on GPA_MFP12 and EBI_HB_EN[5] (ALT_MFP[21]) and EBI_EN (ALT_MFP[11]). EBI_HB_EN[5] [12] GPA_MFP12 PA.11 Pin Function Selection The pin function depends on GPA_MFP11 and EBI_EN (ALT_MFP[11]). EBI_EN [11] GPA_MFP11 PA.10 Pin Function Selection The pin function depends on GPA_MFP10 and EBI_EN (ALT_MFP[11]) ...
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... NuMicro™ NUC100 Series Technical Reference Manual EBI_EN PA.5 Pin Function Selection The pin function depends on GPA_MFP5 and EBI_HB_EN[0] (ALT_MFP[16]) and EBI_EN (ALT_MFP[11]). EBI_HB_EN[0] [5] GPA_MFP5 PA.4 Pin Function Selection The pin function depends on GPA_MFP4 and EBI_HB_EN[1] (ALT_MFP[17]) and EBI_EN (ALT_MFP[11]). EBI_HB_EN[1] ...
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... NuMicro™ NUC100 Series Technical Reference Manual EBI_EN (ALT_MFP[11]). EBI_HB_EN[ PA.0 Pin Function Selection 1 = The ADC0 (Analog-to-Digital converter channel 0) function is selected to the pin [0] GPA_MFP0 PA The GPIOA[0] is selected to the pin PA.0 EBI_EN GPA_MFP[1] PA.1 function x 0 GPIO 0 1 ADC1 (ADC ADC1 (ADC) ...
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... NuMicro™ NUC100 Series Technical Reference Manual Multiple Function Pin GPIOB Control Register (GPB_MFP) Register Offset R/W Description GCR_BA+0x34 R/W GPIOB Multiple Function and Input Type Control Register GPB_MFP Bits Descriptions 1 = Enable GPIOB[15:0] I/O input Schmitt Trigger function [31:16] GPB_TYPEn 0 = Disable GPIOB[15:0] I/O input Schmitt Trigger function PB ...
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... NuMicro™ NUC100 Series Technical Reference Manual PB.11 Pin Function Selection The pin function depends on GPB_MFP11 and PB11_PWM4 (ALT_MFP[4]). PB11_PWM4 [11] GPB_MFP11 PB.10 Pin Function Selection The pin function depends on GPB_MFP10 and PB10_S01 (ALT_MFP[0]). PB10_S01 [10] GPB_MFP10 PB.9 Pin Function Selection The pin function depends on GPB_MFP9 and PB9_S11 (ALT_MFP[1]). ...
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... NuMicro™ NUC100 Series Technical Reference Manual 0 1 PB. 5 Pin Function Selection [ The UART1 TXD function is selected to the pin PB.5 GPB_MFP5 0 = The GPIOB[5] is selected to the pin PB.5 PB.4 Pin Function Selection [ The UART1 RXD function is selected to the pin PB.4 GPB_MFP4 0 = The GPIOB[4] is selected to the pin PB.4 PB ...
Page 139
... NuMicro™ NUC100 Series Technical Reference Manual Multiple Function Pin GPIOC Control Register (GPC_MFP) Register Offset R/W Description GCR_BA+0x38 R/W GPIOC Multiple Function and Input Type Control Register GPC_MFP Bits Descriptions 1 = Enable GPIOC[n] I/O input Schmitt Trigger function [31:16] GPC_TYPEn 0 = Disable GPIOC[n] I/O input Schmitt Trigger function PC ...
Page 140
... NuMicro™ NUC100 Series Technical Reference Manual 1 = The SPI1 MOSI0 (master output, slave input pin-0) function is selected to the pin PC. The GPIOC[11] is selected to the pin PC.11 PC.10 Pin Function Selection 1 = The SPI1 MISO0 (master input, slave output pin-0) function is selected to the pin ...
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... NuMicro™ NUC100 Series Technical Reference Manual PC2_I2SDO PC.2 Pin Function Selection Bits PC2_I2SDI (ALT_MFP[7]) and GPC_MFP[2] determine the PC.2 function. PC2_I2SDI [2] GPC_MFP2 PC.1 Pin Function Selection Bits PC1_I2SBCLK (ALT_MFP[6]) and GPC_MFP[1] determine the PC.1 function. PC1_I2SBCLK [1] GPC_MFP1 PC.0 Pin Function Selection Bits PC0_I2SLRCLK (ALT_MFP[5]) and GPC_MFP[0] determine the PC ...
Page 142
... NuMicro™ NUC100 Series Technical Reference Manual Multiple Function Pin GPIOD Control Register (GPD_MFP) Register Offset R/W Description GCR_BA+0x3C R/W GPIOD Multiple Function and Input Type Control Register GPD_MFP Bits Descriptions 1 = Enable GPIOD[15:0] I/O input Schmitt Trigger function [31:16] GPD_TYPEn 0 = Disable GPIOD[15:0] I/O input Schmitt Trigger function PD ...
Page 143
... NuMicro™ NUC100 Series Technical Reference Manual 0 = The GPIOD[10] is selected to the pin PD.10 PD.9 Pin Function Selection (Medium Density Only) [ The SPI3 SPICLK function is selected to the pin PD.9 GPD_MFP9 0 = The GPIOD[9] is selected to the pin PD.9 PD.8 Pin Function Selection (Medium Density Only) ...
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... NuMicro™ NUC100 Series Technical Reference Manual 1 = The SPI2 SS20 function is selected to the pin PD The GPIOD[0] is selected to the pin PD.0 - 144 - Publication Release Date: Dec. 22, 2010 Revision V1.06 ...
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... NuMicro™ NUC100 Series Technical Reference Manual Multiple Function Pin GPIOE Control Register (GPE_MFP) Register Offset R/W Description GCR_BA+0x40 R/W GPIOE Multiple Function and Input Type Control Register GPE_MFP In this register, Low Density only has GPE_TYPE5 register bit Reserved GPE_MFP5 Bits ...
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... NuMicro™ NUC100 Series Technical Reference Manual Alternative Multiple Function Pin Control Register (ALT_MFP) Register Offset R/W Description GCR_BA+0x50 R/W Alternative Multiple Function Pin Control Register ALT_MFP EBI_nWRH_E EBI_nWRL_E Reserved PC1_I2SBCL PC0_I2SLRC PC2_I2SDI K LK Bits Descriptions [31:24] Reserved Reserved EBI_HB_EN is use to switch GPIO function to EBI address/data bus high byte (AD[15:8]), EBI_HB_EN, EBI_EN and corresponding GPx_MFP[y] determine the Px ...
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... NuMicro™ NUC100 Series Technical Reference Manual 1 Bits EBI_HB_EN[4], EBI_EN and GPA_MFP[1] determine the PA.1 function. EBI_HB_EN[4] x [20] EBI_HB_EN[ Bits EBI_HB_EN[3], EBI_EN and GPA_MFP[2] determine the PA.2 function. EBI_HB_EN[3] x [19] EBI_HB_EN[ Bits EBI_HB_EN[2], EBI_EN and GPA_MFP[3] determine the PA.3 function. EBI_HB_EN[2] ...
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... NuMicro™ NUC100 Series Technical Reference Manual Bits EBI_nWRL_EN, EBI_EN and GPB_MFP[2] determine the PB.2 function. EBI_nWRL_EN x [13] EBI_nWRL_EN Bits EBI_MCLK_EN, EBI_EN and GPC_MFP[8] determine the PC.8 function. EBI_MCLK_EN x [12] EBI_MCLK_EN EBI_EN is use to switch GPIO function to EBI function (AD[15:0], ALE, RE, WE, CS, ...
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... NuMicro™ NUC100 Series Technical Reference Manual 0 1 EBI_EN GPC_MFP[15] PC.15 function EBI_EN GPC_MFP[14] PC.14 function EBI_EN GPB_MFP[13] PB.13 function EBI_EN PB12_CLKO EBI_EN GPA_MFP[11] PA.11 function EBI_EN GPA_MFP[10] PA.10 function EBI_EN GPB_MFP[6] - 149 - 1 CPP0 (CMP) 1 AD4 (EBI AD bus bit 4) 0 GPIO ...
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... NuMicro™ NUC100 Series Technical Reference Manual EBI_EN Bits PB12_CLKO, GPB_MFP[12] and EBI_EN (ALT_MFP[11]) determine the PB.12 function. EBI_EN x [10] PB12_CLKO Bits PA15_I2SMCLK and GPA_MFP[15] determine the PA.15 function. PA15_I2SMCLK [9] x PA15_I2SMCLK 0 1 Bits PC2_I2SDO and GPC_MFP[3] determine the PC.3 function. ...
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... NuMicro™ NUC100 Series Technical Reference Manual PC0_I2SLRCLK Bits PB11_PWM4 and GPB_MFP[11] determine the PB.11 function. PB11_PWM4 x [4] PB11_PWM4 0 1 Bits PB14_S31 and GPB_MFP[14] determine the PB.14 function. PB14_S31 x [3] PB14_S31 0 1 Bits PA7_S21, GPA_MFP[7] and EBI_EN (ALT_MFP[11]).determine the PA.7 function. ...
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... NuMicro™ NUC100 Series Technical Reference Manual Register Write-Protection Control Register (REGWRPROT) Some of the system control registers need to be protected to avoid inadvertent write and disturb the chip operation. These system control registers are protected after the power on reset till user to disable register protection. For user to program these protected registers, a register protection disable sequence needs to be followed by a special programming. The register protection disable sequence is writing the data “ ...
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... NuMicro™ NUC100 Series Technical Reference Manual PORCR: address 0x5000_0024 PWRCON: address 0x5000_0200 (bit[6] is not protected for power wake-up interrupt clear) APBCLK bit[0]: address 0x5000_0208 (bit[0] is watch dog clock enable) CLKSEL0: address 0x5000_0210 (for HCLK and CPU STCLK clock source select) ...
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... NuMicro™ NUC100 Series Technical Reference Manual 5.2.6 System Timer (SysTick) The Cortex-M0 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used as a Real Time Operating System (RTOS) tick timer simple counter. ...
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... NuMicro™ NUC100 Series Technical Reference Manual 5.2.6.1 System Timer Control Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W SCS_BA = 0xE000_E000 SCS_BA+0x10 R/W SYST_CSR SCS_BA+0x14 R/W SYST_RVR SCS_BA+0x18 R/W SYST_CVR Description SysTick Control and Status Register ...
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... NuMicro™ NUC100 Series Technical Reference Manual 5.2.6.2 System Timer Control Register Description SysTick Control and Status （SYST_CSR） Register Offset R/W SCS_BA+0x10 R/W SYST_CSR Reserved Bits Descriptions [31:17] Reserved Reserved Returns 1 if timer counted to 0 since last time this register was read. ...
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... NuMicro™ NUC100 Series Technical Reference Manual SysTick Reload Value Register （SYST_RVR） Register Offset R/W Description SCS_BA+0x14 R/W SysTick Reload Value Register SYST_RVR Bits Descriptions [31:24] Reserved Reserved [23:0] Value to load into the Current Value register when the counter reaches 0. ...
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... NuMicro™ NUC100 Series Technical Reference Manual SysTick Current Value Register （SYST_CVR） Register Offset R/W Description SCS _BA+0x18 R/W SysTick Current Value Register SYST_CVR Bits Descriptions [31:24] Reserved Reserved Current counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection ...
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... NuMicro™ NUC100 Series Technical Reference Manual 5.2.7 Nested Vectored Interrupt Controller (NVIC) Cortex-M0 provides an interrupt controller as an integral part of the exception mode, named as “Nested Vectored Interrupt Controller (NVIC)” closely coupled to the processor kernel and provides following features: Nested and Vectored interrupt support ...
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... Exception Model and System Interrupt Map Table 5-2 lists the exception model supported by NuMicro™ NUC100 Series. Software can set four levels of priority on some of these exceptions as well as on all interrupts. The highest user- configurable priority is denoted as “0” and the lowest priority is denoted as “3”. The default priority of all the user-configurable interrupts is “ ...
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... NuMicro™ NUC100 Series Technical Reference Manual 27 11 TMR3_INT 28 12 UART02_INT 29 13 UART1_INT 30 14 SPI0_INT 31 15 SPI1_INT 32 16 SPI2_INT 33 17 SPI3_INT 34 18 I2C0_INT 35 19 I2C1_INT 36 20 CAN0_INT 37 21 Reserved 38 22 Reserved 39 23 USB_INT 40 24 PS2_INT 41 25 ACMP_INT 42 26 PDMA_INT 43 27 I2S_INT ...
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... NuMicro™ NUC100 Series Technical Reference Manual 5.2.7.2 Vector Table When any interrupts is accepted, the processor will automatically fetch the starting address of the interrupt service routine (ISR) from a vector table in memory. For ARMv6-M, the vector table base address is fixed at 0x00000000. The vector table contains the initialization value for the stack pointer on reset, and the entry point addresses for all exception handlers ...
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... NuMicro™ NUC100 Series Technical Reference Manual 5.2.7.4 NVIC Control Registers R: read only, W: write only, R/W: both read and write Register Offset R/W SCS_BA = 0xE000_E000 SCS_BA+0x100 R/W NVIC_ISER SCS_BA+0x180 R/W NVIC_ICER SCS_BA+0x200 R/W NVIC_ISPR SCS_BA+0x280 R/W NVIC_ICPR SCS_BA+0x400 R/W NVIC_IPR0 SCS_BA+0x404 ...
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... NuMicro™ NUC100 Series Technical Reference Manual IRQ0 ~ IRQ31 Set-Enable Control Register （NVIC_ISER） Register Offset R/W Description SCS _BA+0x100 R/W IRQ0 ~ IRQ31 Set-Enable Control Register NVIC_ISER Bits Descriptions Enable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). ...
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... NuMicro™ NUC100 Series Technical Reference Manual IRQ0 ~ IRQ31 Clear-Enable Control Register (NVIC_ICER) Register Offset R/W Description SCS _BA+0x180 R/W IRQ0 ~ IRQ31 Clear-Enable Control Register NVIC_ICER Bits Descriptions Disable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). ...
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... NuMicro™ NUC100 Series Technical Reference Manual IRQ0 ~ IRQ31 Set-Pending Control Register （NVIC_ISPR） Register Offset R/W Description SCS _BA+0x200 R/W IRQ0 ~ IRQ31 Set-Pending Control Register NVIC_ISPR Bits Descriptions Writing bit to set pending state of the associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47) ...
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... NuMicro™ NUC100 Series Technical Reference Manual IRQ0 ~ IRQ31 Clear-Pending Control Register （NVIC_ICPR） Register Offset R/W Description SCS _BA+0x280 R/W IRQ0 ~ IRQ31 Clear-Pending Control Register NVIC_ICPR Bits Descriptions Writing bit to remove the pending state of associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47) ...
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... NuMicro™ NUC100 Series Technical Reference Manual IRQ0 ~ IRQ3 Interrupt Priority Register （NVIC_IPR0） Register Offset R/W Description SCS _BA+0x400 R/W IRQ0 ~ IRQ3 Interrupt Priority Control Register NVIC_IPR0 PRI_3 PRI_2 PRI_1 PRI_0 Bits Descriptions Priority of IRQ3 [31:30] PRI_3 “0” denotes the highest priority and “3” denotes lowest priority ...
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... NuMicro™ NUC100 Series Technical Reference Manual IRQ4 ~ IRQ7 Interrupt Priority Register （NVIC_IPR1） Register Offset R/W Description SCS _BA+0x404 R/W IRQ4 ~ IRQ7 Interrupt Priority Control Register NVIC_IPR1 PRI_7 PRI_6 PRI_5 PRI_4 Bits Descriptions Priority of IRQ7 [31:30] PRI_7 “0” denotes the highest priority and “3” denotes lowest priority ...
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... NuMicro™ NUC100 Series Technical Reference Manual IRQ8 ~ IRQ11 Interrupt Priority Register （NVIC_IPR2） Register Offset R/W Description SCS _BA+0x408 R/W IRQ8 ~ IRQ11 Interrupt Priority Control Register NVIC_IPR2 PRI_11 PRI_10 PRI_9 PRI_8 Bits Descriptions Priority of IRQ11 [31:30] PRI_11 “0” denotes the highest priority and “3” denotes lowest priority ...
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... NuMicro™ NUC100 Series Technical Reference Manual IRQ12 ~ IRQ15 Interrupt Priority Register （NVIC_IPR3） Register Offset R/W Description SCS _BA+0x40C R/W IRQ12 ~ IRQ15 Interrupt Priority Control Register NVIC_IPR3 PRI_15 PRI_14 PRI_13 PRI_12 Bits Descriptions Priority of IRQ15 [31:30] PRI_15 “0” denotes the highest priority and “3” denotes lowest priority ...
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... NuMicro™ NUC100 Series Technical Reference Manual IRQ16 ~ IRQ19 Interrupt Priority Register （NVIC_IPR4） Register Offset R/W Description SCS _BA+0x410 R/W IRQ16 ~ IRQ19 Interrupt Priority Control Register NVIC_IPR4 PRI_19 PRI_18 PRI_17 PRI_16 Bits Descriptions Priority of IRQ19 [31:30] PRI_19 “0” denotes the highest priority and “3” denotes lowest priority ...
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... NuMicro™ NUC100 Series Technical Reference Manual IRQ20 ~ IRQ23 Interrupt Priority Register （NVIC_IPR5） Register Offset R/W Description SCS _BA+0x414 R/W IRQ20 ~ IRQ23 Interrupt Priority Control Register NVIC_IPR5 PRI_23 PRI_22 PRI_21 PRI_20 Bits Descriptions Priority of IRQ23 [31:30] PRI_23 “0” denotes the highest priority and “3” denotes lowest priority ...
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... NuMicro™ NUC100 Series Technical Reference Manual IRQ24 ~ IRQ27 Interrupt Priority Register （NVIC_IPR6） Register Offset R/W Description SCS _BA+0x418 R/W IRQ24 ~ IRQ27 Interrupt Priority Control Register NVIC_IPR6 PRI_27 PRI_26 PRI_25 PRI_24 Bits Descriptions Priority of IRQ27 [31:30] PRI_27 “0” denotes the highest priority and “3” denotes lowest priority ...
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... NuMicro™ NUC100 Series Technical Reference Manual IRQ28 ~ IRQ31 Interrupt Priority Register （NVIC_IPR7） Register Offset R/W Description SCS _BA+0x41C R/W IRQ28 ~ IRQ31 Interrupt Priority Control Register NVIC_IPR7 PRI_31 PRI_30 PRI_29 PRI_28 Bits Descriptions Priority of IRQ31 [31:30] PRI_31 “0” denotes the highest priority and “3” denotes lowest priority ...
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... Interrupt Source Control Registers Besides the interrupt control registers associated with the NVIC, NuMicro™ NUC100 Series also implement some specific control registers to facilitate the interrupt functions, including “interrupt source identification”, ”NMI source selection” and “interrupt test mode”. They are described as below ...
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... NuMicro™ NUC100 Series Technical Reference Manual IRQ23_SRC INT_BA+0x5C R IRQ23 (USBD) interrupt source identity IRQ24_SRC INT_BA+0x60 R IRQ24 (PS2) interrupt source identity IRQ25_SRC INT_BA+0x64 R IRQ25 (ACMP) interrupt source identity IRQ26_SRC INT_BA+0x68 R IRQ26 (PDMA) interrupt source identity IRQ27_SRC INT_BA+0x6C R IRQ27 (I2S) interrupt source identity ...
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... NuMicro™ NUC100 Series Technical Reference Manual Interrupt Source Identity Register (IRQn_SRC) Register Offset R/W Description IRQ0 (BOD) interrupt source identity INT_BA+0x00 …….. R ： IRQn_SRC INT_BA+0x7C IRQ31 (RTC) interrupt source identity Reserved Bits Address INT-Num Descriptions [2:0] INT_BA+0x00 0 [2:0] INT_BA+0x04 ...
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... NuMicro™ NUC100 Series Technical Reference Manual [3:0] INT_BA+0x1C 7 [2:0] INT_BA+0x20 8 [2:0] INT_BA+0x24 9 [2:0] INT_BA+0x28 10 [2:0] INT_BA+0x2C 11 [2:0] INT_BA+0x30 12 [2:0] INT_BA+0x34 13 [2:0] INT_BA+0x38 14 [2:0] INT_BA+0x3C 15 [2:0] INT_BA+0x40 16 [2:0] INT_BA+0x44 17 [2:0] INT_BA+0x48 18 [2:0] INT_BA+0x4C 19 Bit0: PWM0_INT Bit3: PWM7_INT Bit2: PWM6_INT Bit1: PWM5_INT ...
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... NuMicro™ NUC100 Series Technical Reference Manual [2:0] INT_BA+0x50 20 [2:0] INT_BA+0x54 21 [2:0] INT_BA+0x58 22 [2:0] INT_BA+0x5C 23 [2:0] INT_BA+0x60 24 [2:0] INT_BA+0x64 25 [2:0] INT_BA+0x68 26 [2:0] INT_BA+0x6C 27 [2:0] INT_BA+0x70 28 [2:0] INT_BA+0x74 29 [2:0] INT_BA+0x78 30 [2:0] INT_BA+0x7C 31 NMI Interrupt Source Select Control Register (NMI_SEL) Register Offset R/W ...
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... NuMicro™ NUC100 Series Technical Reference Manual Reserved Bits Descriptions [31:5] Reserved Reserved NMI interrupt source select [4:0] NMI_SEL The NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMI_SEL Reserved Reserved NMI_SEL[4:0] Publication Release Date: Oct 22, 2010 - 181 - ...
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... NuMicro™ NUC100 Series Technical Reference Manual MCU Interrupt Request Source Register (MCU_IRQ) Register Offset R/W Description INT_BA+0x84 R/W MCU Interrupt Request Source Register MCU_IRQ Bits Descriptions MCU IRQ Source Register The MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0 ...
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... NuMicro™ NUC100 Series Technical Reference Manual 5.2.8 System Control Register Cortex-M0 status and operating mode control are managed System Control Registers. Including CPUID, Cortex-M0 interrupt priority and Cortex-M0power management can be controlled through these system control register For more detailed information, please refer to the documents “ARM ® ...
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... NuMicro™ NUC100 Series Technical Reference Manual CPUID Register (CPUID) Register Offset R/W Description SCS_BA+0xD00 R CPUID Register CPUID Reserved PARTNO[3:0] Bits Descriptions [31:24] Implementer code assigned by ARM. ( ARM = 0x41) IMPLEMENTER [23:20] Reserved Reserved [19:16] Reads as 0xC for ARMv6-M parts PART [15:4] Reads as 0xC20 ...
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... NuMicro™ NUC100 Series Technical Reference Manual Interrupt Control State Register (ICSR) Register Offset R/W Description SCS_BA+0xD04 R/W Interrupt Control State Register ICSR NMIPENDSE Reserved ISRPREEMP ISRPENDING Reserved VECTPENDING[3: Bits Descriptions Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will [31] activate as soon registered ...
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... NuMicro™ NUC100 Series Technical Reference Manual Value > the exception number for the current executing exception. This is a read only bit. - 186 - Publication Release Date: Dec. 22, 2010 Revision V1.06 ...
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... NuMicro™ NUC100 Series Technical Reference Manual Application Interrupt and Reset Control Register (AIRCR) Register Offset R/W Description SCS_BA+0xD0C R/W Application Interrupt and Reset Control Register AIRCR Reserved Bits Descriptions When write this register, this field should be 0x05FA, otherwise the write action will be ...
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... NuMicro™ NUC100 Series Technical Reference Manual System Control Register (SCR) Register Offset R/W Description SCS_BA+0xD10 R/W System Control Register SCR Reserved Bits Descriptions [31:5] Reserved Reserved When enabled, interrupt transitions from Inactive to Pending are included in the list of [4] SEVONPEND wakeup events for the WFE instruction. ...
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... NuMicro™ NUC100 Series Technical Reference Manual System Handler Priority Register 2 (SHPR2) Register Offset R/W Description SCS_BA+0xD1C R/W System Handler Priority Register 2 SHPR2 PRI_11 Bits Descriptions Priority of system handler 11 – SVCall [31:30] PRI_11 “0” denotes the highest priority and “3” denotes lowest priority ...
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... NuMicro™ NUC100 Series Technical Reference Manual System Handler Priority Register 3 (SHPR3) Register Offset R/W Description SCS_BA+0xD20 R/W System Handler Priority Register 3 SHPR3 PRI_15 PRI_14 Bits Descriptions Priority of system handler 15 – SysTick [31:30] PRI_15 “0” denotes the highest priority and “3” denotes lowest priority ...
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... NuMicro™ NUC100 Series Technical Reference Manual 5.3 Clock Controller 5.3.1 Overview The clock controller generates the clocks for the whole chip, including system clocks and all peripheral clocks. The clock controller also implements the power control function with the individually clock ON/OFF control, clock source selection and a 4-bit clock divider. The chip will not enter power-down mode until CPU sets the power down enable bit (PWR_DOWN_EN) and Cortex-M0 core executes the WFI instruction ...
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... NuMicro™ NUC100 Series Technical Reference Manual 5.3.3 System Clock & SysTick Clock The system clock has 5 clock sources which were generated from clock generator block. The clock source switch depends on the register HCLK_S (CLKSEL0[2:0]). The block diagram is showed in Figure 5-5. ...
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... NuMicro™ NUC100 Series Technical Reference Manual 5.3.4 Peripherals Clock The peripherals clock had different clock source switch setting which depends on the different peripheral. Please refer the CLKSEL1 and CLKSEL2 register description in 5.3.7. 5.3.5 Power down mode (Deep Sleep Mode) Clock When chip enters into power down mode, system clocks, some clock sources, and some peripheral clocks will be disabled ...
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... NuMicro™ NUC100 Series Technical Reference Manual 5.3.6 Frequency Divider Output This device is equipped a power-of-2 frequency divider which is composed by16 chained divide- by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one multiplexer is reflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided clocks with ...
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... NuMicro™ NUC100 Series Technical Reference Manual 5.3.7 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W CLK_BA = 0x5000_0200 CLK_BA+0x00 R/W PWRCON CLK_BA+0x04 R/W AHBCLK CLK_BA+0x08 R/W APBCLK CLKSTATUS CLK_BA+0x0C R/W CLK_BA+0x10 R/W CLKSEL0 CLK_BA+0x14 R/W ...
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... NuMicro™ NUC100 Series Technical Reference Manual 5.3.8 Register Description Power Down Control Register （PWRCON） Except the BIT[6], all the other bits are protected, program these bits need to write “59h”, “16h”, “88h” to address 0x5000_0100 to disable register protection. Reference the register ...
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... NuMicro™ NUC100 Series Technical Reference Manual 1 = Chip enter the power down mode instant or wait CPU sleep command WFI 0 = Chip operate in normal mode or CPU in idle mode (sleep mode) because of WFI command Power down mode wake up interrupt status Set by “power down wake up event”, it indicates that resume from power down mode” ...
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... NuMicro™ NUC100 Series Technical Reference Manual Register/Instruction PWR_DOWN_EN PD_WAIT_CPU Mode Normal Running Mode 0 IDLE Mode 0 (CPU entry Sleep Mode) Power_down Mode 1 Power_down Mode 1 (CPU entry deep sleep mode) Table 5-5 Power Down Mode Control Table When chip enter power down mode, user can wakeup chip by some interrupt sources. User ...
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... NuMicro™ NUC100 Series Technical Reference Manual AHB Devices Clock Enable Control Register （AHBCLK） These bits for this register are used to enable/disable clock for system clock PDMA clock and EBI clock. Register Offset R/W Description CLK_BA+0x04 R/W AHB Devices Clock Enable Control Register ...
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... NuMicro™ NUC100 Series Technical Reference Manual APB Devices Clock Enable Control Register （APBCLK） These bits of this register are used to enable/disable clock for peripheral controller clocks. Register Offset R/W Description CLK_BA+0x08 R/W APB Devices Clock Enable Control Register APBCLK 31 30 ...