NUMICRO-SDK Nuvoton Technology Corporation of America, NUMICRO-SDK Datasheet - Page 242

• Manufacturer Part Number: NUMICRO-SDK
• Description: KIT EVAUATION NUC100/120/130/140
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r
• Type: MCUr

Specifications of NUMICRO-SDK

• Contents: Board, Cable, CD, Nu-Link
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: NUC100, NUC120, NUC130, NUC140

5.5.3.3
5.5.3.4
Set GPIOx_PMD (PMDn[1:0]) to 10b the GPIOx port [n] pin is in Open-Drain mode and the digital
output function of I/O pin supports only sink current capability, an additional pull-up register is
needed for driving high state. If the bit value in the corresponding bit [n] of GPIOx_DOUT is 0, the
pin drive a “low” output on the pin. If the bit value in the corresponding bit [n] of GPIOx_DOUT is
1, the pin output drives high that is controlled by external pull high resistor.
Set GPIOx_PMD (PMDn[1:0]) to 11b the GPIOx port [n] pin is in Quasi-bidirectional mode and the
I/O pin supports digital output and input function at the same time but the source current is only
up to hundreds uA. Before the digital input function is performed the corresponding bit in
GPIOx_DOUT must be set to 1. The quasi-bidirectional output is common on the 80C51 and most
of its derivatives. If the bit value in the corresponding bit [n] of GPIOx_DOUT is 0, the pin drive a
“low” output on the pin. If the bit value in the corresponding bit [n] of GPIOx_DOUT is 1, the pin
will check the pin value. If pin value is high, no action takes. If pin state is low, then pin will drive
strong high with 2 clock cycles on the pin and then disable the strong output drive and then the
pin status is control by internal pull-up resistor. Note that the source current capability in quasi-
bidirectional mode is only about 200uA to 30uA for VDD is form 5.0V to 2.5V.
Port Latch
Data
Open-Drain Mode Explanation
Quasi-bidirectional Mode Explanation
NuMicro™ NUC100 Series Technical Reference Manual
Port Latch
Data
Clock Delay
Input Data
Figure 5-16 Quasi-bidirectional I/O Mode
2 CPU
Figure 5-15 Open-Drain Output
N
Input Data
- 242 -
N
P
Publication Release Date: Dec. 22, 2010
Strong
P
VDD
Weak
Very
Port Pin
P
Revision V1.06
Weak
Port