LIS3LV02DLTR STMicroelectronics, LIS3LV02DLTR Datasheet
LIS3LV02DLTR
Specifications of LIS3LV02DLTR
LIS3LV02DLTR
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LIS3LV02DLTR Summary of contents
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... Table 1. Device summary Operating temperature Order code LIS3LV02DL LIS3LV02DLTR January 2008 The LIS3LV02DL has a user selectable full scale of ±2g, ±6g and it is capable of measuring acceleration over a bandwidth of 640 Hz for all axes. The device bandwidth may be selected accordingly to the application requirements. ...
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Content Content 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 Block ...
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LIS3LV02DL 7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Content 8 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.1 Mechanical characteristics at 25° ...
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LIS3LV02DL List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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LIS3LV02DL Table 49. Register description (2Dh ...
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Block diagram and pin description 1 Block diagram and pin description 1.1 Block diagram Figure 1. Block diagram a SELF TEST 1.2 LGA-16 pin description Figure 2. Pin connection Z DIRECTION OF THE DETECTABLE ACCELERATIONS Table 2. Pin description Pin# ...
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LIS3LV02DL Table 2. Pin description Pin Name 2 SDA Serial Data (SDA) SDI/ SPI Serial Data Input (SDI) SDO 3-wire Interface Serial Data Output ...
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Mechanical and electrical specifications 2 Mechanical and electrical specifications 2.1 Mechanical characteristics Table 3. Mechanical characteristics @ Vdd=3.3 V, T=25 °C unless otherwise noted Symbol Parameter FS Measurement range Dres Device resolution So Sensitivity Sensitivity change vs TCSo temperature Zero-g ...
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LIS3LV02DL Table 3. Mechanical characteristics @ Vdd=3.3 V, T=25 °C unless otherwise noted (continued) Symbol Parameter NL Non Linearity CrAx Cross axis V Self test output change st (9) BW System Bandwidth Operating Temperature Top Range Wh Product Weight 1. ...
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Mechanical and electrical specifications Table 4. Mechanical characteristics @ Vdd=2.5 V, T=25 °C unless otherwise noted Symbol Parameter FS Measurement range Dres Device resolution So Sensitivity Sensitivity change vs TCSo temperature Zero-g level offset Off (4),(5) accuracy Zero-g level offset ...
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LIS3LV02DL Table 4. Mechanical characteristics @ Vdd=2.5 V, T=25 °C unless otherwise noted (continued) Symbol Parameter NL Non linearity CrAx Cross axis V Self test output change st (9) BW System bandwidth Top Operating temperature range Wh Product weight 1. ...
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Mechanical and electrical specifications 2.2 Electrical characteristics Table 5. Electrical characteristics @ Vdd=3.3 V, T=25 °C unless otherwise noted Symbol Parameter Vdd Supply voltage Vdd_IO I/O pads supply voltage Idd Supply current Current consumption in IddPdn Power-down mode Digital High ...
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LIS3LV02DL 2.3 Communication interface characteristics 2.3.1 SPI - serial peripheral interface Subject to general operating conditions for Vdd and Top. Table 6. SPI Slave Timing Values Symbol tc(SPC) fc(SPC) tsu(CS) th(CS) tsu(SI) th(SI) tv(SO) th(SO) tdis(SO) 1. Values are guaranteed ...
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Mechanical and electrical specifications 2 2.3 Inter IC control interface Subject to general operating conditions for Vdd and Top. Table 7. I2C slave timing values Symbol Parameter f SCL clock frequency (SCL) t SCL clock low time ...
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LIS3LV02DL 2.4 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to ...
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Mechanical and electrical specifications 2.5 Terminology 2.5.1 Sensitivity Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing ...
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LIS3LV02DL 3 Functionality The LIS3LV02DL is a high performance, low-power, digital output 3-axis linear accelerometer packaged in an LGA package. The complete device includes a sensing element and an IC interface able to take the information from the sensing element ...
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Functionality 3.3 Factory calibration The IC interface is factory calibrated for sensitivity (So) and Zero-g level (Off). The trimming values are stored inside the device by a non volatile structure. Any time the device is turned on, the trimming parameters ...
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LIS3LV02DL 4 Application hints Figure 5. LIS3LV02DL electrical connection Vdd_IO GND The device core is supplied through Vdd line while the I/O pads are supplied through Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF Al) should be ...
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Digital interfaces 5 Digital interfaces The registers embedded inside the LIS3LV02DL may be accessed through both the I SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The serial interfaces are ...
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LIS3LV02DL 2 5.1 operation The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. ...
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Digital interfaces Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. DATA is transferred with the Most Significant bit (MSb) first receiver can’t receive another ...
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LIS3LV02DL bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip will drive SDO at the start of bit 8. bit ...
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Digital interfaces Figure 8. Multiple bytes SPI read protocol (2 bytes example) CS SPC SDI RW MS SDO 5.2.2 SPI write Figure 9. SPI write protocol CS SPC SDI The SPI Write command is performed with 16 clock pulses. Multiple ...
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LIS3LV02DL 5.2.3 SPI Read in 3-wires mode 3-wires mode is entered by setting to ‘1’ bit SIM (SPI Serial Interface Mode selection) in CTRL_REG2. Figure 11. SPI read protocol in 3-wires mode CS SPC SDI/O The SPI Read command is ...
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Register mapping 6 Register mapping The table given below provides a listing of the 8 bit registers embedded in the device and the related addresses. Table 15. Registers address map Register name Type rw WHO_AM_I r rw OFFSET_X rw OFFSET_Y ...
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LIS3LV02DL Table 15. Registers address map (continued) Register name Type FF_WU_THS_H rw FF_WU_DURATION rw DD_CFG rw DD_SRC rw DD_ACK r DD_THSI_L rw DD_THSI_H rw DD_THSE_L rw DD_THSE_H rw Registers marked as Reserved must not be changed. The writing to those ...
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Register description 7 Register description The device contains a set of registers which are used to control its behavior and to retrieve acceleration data. The registers necessary to change their value for normal device operation. 7.1 WHO_AM_I (0Fh) Table 16. ...
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LIS3LV02DL Table 23. Register description (18h) OZ7, OZ0 Digital Offset Trimming for Z-Axis 7.5 GAIN_X (19h) Table 24. Register (19h) GX7 GX6 Table 25. Register description (19h) GX7, GX0 Digital Gain Trimming for X-Axis 7.6 GAIN_Y (1Ah) Table 26. Register ...
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Register description Table 31. Register description (continued) (20h) Self Test Enable ST (0: normal mode; 1: self-test active) Z-axis enable Zen (0: axis off; 1: axis on) Y-axis enable Yen (0: axis off; 1: axis on) X-axis enable Xen (0: ...
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LIS3LV02DL Table 33. Register description (continued) (21h) SPI Serial Interface Mode selection SIM (0: 4-wire interface; 1: 3-wire interface) Data Alignment Selection DAS (0: 12 bit right justified bit left justified) FS bit is used to select Full ...
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Register description 7.10 CTRL_REG3 (22h) Table 34. Register (22h) ECK HPDD Table 35. Register description (22h) External Clock. Default value: 0 ECK (0: clock from internal oscillator; 1: clock from external pad) High Pass filter enabled for Direction Detection. Default ...
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LIS3LV02DL Table 37. Register description (continued) (27h) ZYXDA X, Y and Z axis new Data Available ZDA Z axis new Data Available YDA Y axis new Data Available XDA X axis new Data Available The content of this register is ...
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Register description Table 43. Register description (2Ah) YD7, YD0 Y axis acceleration data LSB In Big Endian Mode (bit BLE in CTRL_REG2 set to ‘1’) the content of this register is the MSB acceleration data and depends on bit DAS ...
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LIS3LV02DL In Big Endian Mode (bit BLE in CTRL_REG2 set to ‘1’) the content of this register is the LSB acceleration data. 7.19 FF_WU_CFG (30h) Table 50. Register (30h) AOI LIR Table 51. Register description (30h) And/Or combination of Interrupt ...
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Register description Table 53. Register description (31h) Interrupt Active. Default value (0: no interrupt has been generated; 1: one or more interrupt events have been generated) Z High. Default value (0: no interrupt High ...
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LIS3LV02DL 7.24 FF_WU_DURATION (36h) Table 58. Register (36h) FWD7 FWD6 Table 59. Register description (36h) FWD7, FWD0 This register sets the minimum duration of the free-fall/wake-up event to be recognized. 7.25 DD_CFG (38h) Table 60. Register (38h) IEND LIR Table ...
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Register description Table 61. Register description (continued) (38h) Enable interrupt generation on X High event. Default value: 0 XHIE (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on X ...
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LIS3LV02DL 7.27 DD_ACK (3Ah) Dummy register. If LIR bit in DD_CFG register is set to ‘1’, a reading at this address allows the DD_SRC register refresh. Read data is not significant. 7.28 DD_THSI_L (3Ch) Table 64. Register (3Ch) THSI7 THSI6 ...
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Typical performance characteristics 8 Typical performance characteristics 8.1 Mechanical characteristics at 25°C Figure 12. X-axis zero-g level at 3 −60 −40 −20 0 Zero−g Level Offset [mg] Figure ...
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LIS3LV02DL Figure 16. Z-axis zero-g level at 3 −60 −40 −20 0 Zero−g Level Offset [mg] 8.2 Mechanical characteristics derived from measurement in the -40°C to +85°C temperature range Figure 18. X-axis zero-g ...
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Typical performance characteristics Figure 20. Y-axis zero-g level change vs. temperature at 3 −1 −0.8 −0.6 −0.4 −0.2 0 Zero−g Level drift [mg/ Figure 22. Z-axis zero-g level change vs. ...
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LIS3LV02DL Figure 26. Current consumption in Power- Down mode (Vdd=3 −5 −2.5 0 Current consumption [uA] Typical performance characteristics Figure 27. Current consumption in operational mode (Vdd=3 ...
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Package information 9 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the ...
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LIS3LV02DL 10 Revision history Table 72. Document revision history Date 15-Feb-2006 15-Jan-2008 Revision 1 Initial release. Added two new sections: Section 2.3: Communication interface characteristics 2 Typical performance Content reworked to improve readability Revision history Changes and characteristics. Section 8: ...
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