DP83815DUJB National Semiconductor, DP83815DUJB Datasheet - Page 76
![IC, ENET CTRL 10BASET, 100MBPS, LBGA-160](/photos/19/0/190058/4551706_sml.jpg)
DP83815DUJB
Manufacturer Part Number
DP83815DUJB
Description
IC, ENET CTRL 10BASET, 100MBPS, LBGA-160
Manufacturer
National Semiconductor
Datasheet
1.DP83815DUJB.pdf
(108 pages)
Specifications of DP83815DUJB
Data Rate
100Mbps
Ethernet Type
10BASE-T
Supply Current
170mA
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
0°C To +70°C
No. Of Pins
160
Termination Type
SMD
Filter Terminals
SMD
Rohs Compliant
No
Data Rate Max
100Mbps
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DP83815DUJB
Manufacturer:
NS
Quantity:
996
Company:
Part Number:
DP83815DUJB
Manufacturer:
Texas Instruments
Quantity:
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Part Number:
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Manufacturer:
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Company:
Part Number:
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Manufacturer:
Texas Instruments
Quantity:
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4.0 Register Set
4.3.15 PHY Control Register
15:12
Bit
7:6
4:3
1:0
Bit
6:5
4:0
11
10
8
5
2
9
8
7
FORCE_100_OK Force 100 Mb/s Good Link:
NRZI_BYPASS
BIST_STATUS
PHYADDR[4:0]
BP_STRETCH
BIST_START
PAUSE_STS
SD_OPTION
Bit Name
Bit Name
Reserved
Reserved
Reserved
Reserved
Reserved
PSR_15
Offset: 00E4h
(Continued)
Tag: PHYCR
Reserved
BIST Sequence select: Selects length of LFSR used in BIST
1 = PSR15 selected
0 = PSR9 selected
BIST Test Status: Default: 0, LL/RO
1 = BIST pass
0 = BIST fail. Latched, cleared by write to BIST start bit.
BIST Start: BIST runs continuously until stopped. Minimum time to run should be 1 ms.
1 = BIST start
0 = BIST stop
Bypass LED Stretching:
This will bypass the LED stretching and the LEDs will reflect the internal value.
1 = Bypass LED stretching
0 = Normal operation
Pause Compare Status: Default: 0, RO
0 = Local Device and the Link Partner are not Pause capable
1 = Local Device and the Link Partner are both Pause capable
Reserved
PHY Address: Default: <11111b>, RW
PHY address for the port.
Signal Detect Option:
1 = Enhanced signal detect algorithm
0 = Reduced signal detect algorithm
Reserved: Read as 0
OR’ed with MAC_FORCE_LINK_100 signal.
1 = Forces 100 Mb/s Good Link
0 = Normal 100 Mb/s operation
Reserved: Read as 0
NRZI Bypass Enable:
1 = NRZI Bypass Enabled
0 = NRZI Bypass Disabled
Reserved: Read as 0
Access: Read Write
Size: 16 bits
76
Description
Description
Hard Reset: 003Fh
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