DSPIC30F5011-20I/PTG Microchip Technology, DSPIC30F5011-20I/PTG Datasheet - Page 124

• Manufacturer Part Number: DSPIC30F5011-20I/PTG
• Description: IC, DSC, 16BIT, 66KB, 40MHZ 5.5V TQFP-64
• Manufacturer: Microchip Technology
• Series: DsPIC30Fr

Specifications of DSPIC30F5011-20I/PTG

• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 52
• Flash Memory Size: 66KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC30F5011/5013
18.3.8
The sample clock edge (CSCKE) control bit determines
the sampling edge for the CSCK signal. If the CSCK bit
is cleared (default), data will be sampled on the falling
edge of the CSCK signal. The AC-Link protocols and
most Multi-Channel formats require that data be
sampled on the falling edge of the CSCK signal. If the
CSCK bit is set, data will be sampled on the rising edge
of CSCK. The I
sampled on the rising edge of the CSCK signal.
18.3.9
In most applications, the data transfer begins one
CSCK cycle after the COFS signal is sampled active.
This is the default configuration of the DCI module. An
alternate data alignment can be selected by setting the
DJST control bit in the DCICON1 SFR. When DJST = 1,
data transfers will begin during the same CSCK cycle
when the COFS signal is sampled active.
18.3.10
The TSCON SFR has control bits that are used to
enable up to 16 time slots for transmission. These
control bits are the TSE<15:0> bits. The size of each
time slot is determined by the WS<3:0> word size
selection bits and can vary up to 16 bits.
If a transmit time slot is enabled via one of the TSE bits
(TSEx = 1), the contents of the current transmit shadow
buffer location will be loaded into the CSDO Shift
register and the DCI buffer control unit is incremented
to point to the next location.
During an unused transmit time slot, the CSDO pin will
drive ‘0’s or will be tri-stated during all disabled time
slots depending on the state of the CSDOM bit in the
DCICON1 SFR.
The data frame size in bits is determined by the chosen
data word size and the number of data word elements
in the frame. If the chosen frame size has less than 16
elements, the additional slot enable bits will have no
effect.
Each transmit data word is written to the 16-bit transmit
buffer as left justified data. If the selected word size is
less than 16 bits, then the LSbs of the transmit buffer
memory will have no effect on the transmitted data. The
user should write ‘0’s to the unused LSbs of each
transmit buffer location.
DS70116H-page 124
SAMPLE CLOCK EDGE
CONTROL BIT
DATA JUSTIFICATION
CONTROL BIT
TRANSMIT SLOT ENABLE BITS
2
S protocol requires that data be
18.3.11
The RSCON SFR contains control bits that are used to
enable up to 16 time slots for reception. These control
bits are the RSE<15:0> bits. The size of each receive
time slot is determined by the WS<3:0> word size
selection bits and can vary from 1 to 16 bits.
If a receive time slot is enabled via one of the RSE bits
(RSEx = 1), the shift register contents will be written to
the current DCI receive shadow buffer location and the
buffer control unit will be incremented to point to the
next buffer location.
Data is not packed in the receive memory buffer
locations if the selected word size is less than 16 bits.
Each received slot data word is stored in a separate
16-bit buffer location. Data is always stored in a left
justified format in the receive memory buffer.
18.3.12
The TSE and RSE control bits operate in concert with
the DCI frame sync generator. In the Master mode, a
COFS signal is generated whenever the frame sync
generator is reset. In the Slave mode, the frame sync
generator is reset whenever a COFS pulse is received.
The TSE and RSE control bits allow up to 16
consecutive time slots to be enabled for transmit or
receive. After the last enabled time slot has been
transmitted/received, the DCI will stop buffering data
until the next occurring COFS pulse.
18.3.13
The DCI buffer control unit will be incremented by one
word location whenever a given time slot has been
enabled for transmission or reception. In most cases,
data input and output transfers will be synchronized,
which means that a data sample is received for a given
channel at the same time a data sample is transmitted.
Therefore, the transmit and receive buffers will be filled
with equal amounts of data when a DCI interrupt is
generated.
In some cases, the amount of data transmitted and
received during a data frame may not be equal. As an
example, assume a two-word data frame is used.
Furthermore, assume that data is only received during
slot #0 but is transmitted during slot #0 and slot #1. In
this case, the buffer control unit counter would be
incremented twice during a data frame but only one
receive register location would be filled with data.
RECEIVE SLOT ENABLE BITS
SLOT ENABLE BITS OPERATION
WITH FRAME SYNC
SYNCHRONOUS DATA
TRANSFERS
© 2008 Microchip Technology Inc.