ADSP-BF538BBCZ-5F4 Analog Devices Inc, ADSP-BF538BBCZ-5F4 Datasheet - Page 45

• Manufacturer Part Number: ADSP-BF538BBCZ-5F4
• Description: IC, FLOAT-PT DSP, 16BIT, 533MHZ, BGA-316
• Manufacturer: Analog Devices Inc
• Series: Blackfinr
• Type: Fixed Pointr

Specifications of ADSP-BF538BBCZ-5F4

• No. Of Bits: 16 Bit
• Frequency: 533MHz
• Supply Voltage: 1.25V
• Embedded Interface Type: CAN, I2C, PPI, SPI, TWI, UART
• No. Of I/o's: 54
• Flash Memory Size: 512KB
• Interface: CAN, SPI, SSP, TWI, UART
• Clock Rate: 533MHz
• Non-volatile Memory: FLASH (512 kB)
• On-chip Ram: 148kB
• Voltage - I/o: 3.00V, 3.30V
• Voltage - Core: 1.25V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 316-CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-BFAUDIO-EZEXT - BOARD EVAL AUDIO BLACKFIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Universal Asynchronous Receiver-Transmitter
(UART) Ports—Receive and Transmit Timing
For information on the UART port receive and transmit opera-
tions, see the ADSP-BF538 Blackfin Processor Hardware
Reference.
JTAG Test and Emulation Port Timing
Table 39
Table 39. JTAG Port Timing
1
2
3
4
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
System Inputs=ARDY, BMODE1–0, BR, DATA15–0, DR0PRI, DR0SEC, NMI, PF15–0, PPI_CLK, PPI3–0, SCL1–0, SDA1–0, SCK2–0, MISO2–0, MOSI2–0, SPI1SS,
50 MHz maximum
System Outputs = AMS, AOE, ARE, AWE, ABE, BG, DATA15–0, PF15–0, PC9–5, PPI3-0, SPI1SS, SPI1SEL1, SCK2–0, MISO2–0, MOSI2–0, SPI2SS, SPI2SEL1, RX2–1,
System open-drain outputs: CANRX (when configured as PC1) and PC4.
TCK
STAP
HTAP
SSYS
HSYS
TRSTW
DTDO
DSYS
SPI1SEL1, SPI2SS, SPI2SEL1, RX2–0, TX2–1, DT2PRI, DT2SEC, DR2PRI, DR2SEC, DT3PRI, DT3SEC, TSCLK3–0, DR3PRI, DR3SEC, RSCLK3–0, RFS3–0, TFS3–0,
CANTX, CANRX, RESET, PC9–4, GPW, and TMR2–0.
TX2–0, DT2PRI, DT2SEC, DR2PRI, DR2SEC, DT3PRI, DT3SEC, DR3PRI, DR3SEC, RSCLK3–0, RFS3–0, TSCLK3–0, TFS3–0, CANTX, CLKOUT, SA10, SCAS, SCKE,
SMS, SRAS, SWE, and TMR2–0.
and
OUTPUTS
SYSTEM
SYSTEM
INPUTS
TCK
TMS
TDO
Figure 31
TDI
TCK Period
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK High
System Inputs Hold After TCK High
TRST Pulse Width
TDO Delay from TCK Low
System Outputs Delay After TCK Low
describe JTAG port operations.
2
(Measured in TCK Cycles)
t
DSYS
t
DTDO
t
TCK
t
SSYS
Rev. D | Page 45 of 56 | July 2010
t
1
STAP
3,4
1
Figure 31. JTAG Port Timing
t
HTAP
t
HSYS
ADSP-BF538/ADSP-BF538F
Min
20
4
4
4
6
4
0
Max
10
12
Unit
ns
ns
ns
ns
ns
TCK
ns
ns