LFE2-35E-5FN484C LATTICE SEMICONDUCTOR, LFE2-35E-5FN484C Datasheet - Page 44
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LFE2-35E-5FN484C
Manufacturer Part Number
LFE2-35E-5FN484C
Description
IC, LATTICEECP2 FPGA, 420MHZ, FPBGA-484
Manufacturer
LATTICE SEMICONDUCTOR
Series
LatticeECP2r
Datasheet
1.LFE2-12E-5FN256C.pdf
(385 pages)
Specifications of LFE2-35E-5FN484C
No. Of Logic Blocks
32000
No. Of Macrocells
16000
No. Of Speed Grades
5
No. Of I/o's
331
Clock Management
DLL, PLL
I/o Supply Voltage
3.465V
Total Ram Bits
332Kbit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2-35E-5FN484C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Figure 2-38. LatticeECP2M Banks
LatticeECP2/M devices contain two types of sysI/O buffer pairs.
1. Top (Bank 0 and Bank 1) sysI/O Buffer Pairs (Single-Ended Outputs Only)
2. Bottom (Bank 4 and Bank 5) sysI/O Buffer Pairs (Single-Ended Outputs Only)
The sysI/O buffer pairs in the top banks of the device consist of two single-ended output drivers and two sets of
single-ended input buffers (both ratioed and referenced). One of the referenced input buffers can also be con-
figured as a differential input.
The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive
side of the differential input buffer and the comp (complementary) pad is associated with the negative side of
the differential input buffer.
The sysI/O buffer pairs in the bottom banks of the device consist of two single-ended output drivers and two
V
V REF1(7)
V REF2(7)
V CCIO6
V REF1(6)
V REF2(6)
CCIO7
GND
GND
SERDES
SERDES
Quad
Quad
Bank 0
Bank 5
BOTTOM
TOP
2-41
Bank 1
Bank 4
LatticeECP2/M Family Data Sheet
SERDES
SERDES
Quad
Quad
V CCIO2
V REF1(2)
V REF2(2)
V CCIO3
V REF1(3)
V REF2(3)
V CCIO8
GND
GND
GND
Architecture
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