LCMXO256C-5TN100C LATTICE SEMICONDUCTOR, LCMXO256C-5TN100C Datasheet - Page 204
![MACHXO PLD FLASH, SCRAM 1.8V, 256](/photos/19/0/190054/42334689_sml.jpg)
LCMXO256C-5TN100C
Manufacturer Part Number
LCMXO256C-5TN100C
Description
MACHXO PLD FLASH, SCRAM 1.8V, 256
Manufacturer
LATTICE SEMICONDUCTOR
Series
MachXOr
Datasheet
1.LCMXO1200C-5TN144C.pdf
(244 pages)
Specifications of LCMXO256C-5TN100C
Cpld Type
FLASH
No. Of Macrocells
128
No. Of I/o's
78
Propagation Delay
3.5ns
Global Clock Setup Time
1.3ns
Frequency
600MHz
Supply Voltage Range
1.71V To 3.465V
Operating
RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO256C-5TN100C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
TCK
The test clock pin provides the clock to run the TAP controller, which loads and unloads the data and instruction
registers. TCK can be stopped in either the high or low state and can be clocked at speeds up to the frequency indi-
cated in the
recommended to avoid inadvertent clocking of the TAP controller as V
V
V
JTAG pins please refer to the
but check that the desired voltage is compatible with the ispDOWNLOAD
header.
Figure 12-2. Download Header to MachXO Wiring
Download Cable Pinout
Standard pinouts for the 1x10, 1x8, and 2x5 download headers are shown in the
Sheet. All new ispDOWNLOAD Cables have uncommitted “flywire” connections, so they can be attached to any of
the header styles. Refer to the
BSDL Files
BSDL files for this device can be found on the Lattice Semiconductor web site. The boundary scan ring covers all of
the I/O pins.
Device Wake Up
When configuration is complete (the SRAM has been loaded), the device will wake up in a predictable fashion. The
wake up sequence is driven by, and is synchronous to, an internal clock.
Software Options
Preference Options
Preference options are set by opening the Preference Editor within the ispLEVER
software and selecting the global options tab.
CC
CC
for the internal JTAG logic is supplied by the associated bank’s V
Supply for JTAG
MachXO Family Data
Note: Place a decoupling capacitor close to the connector’s V
standard ceramic capacitor value may be used, for example 0.1 µF, 0.01 µF, etc.
1x10
10
1
2
3
4
5
6
7
8
9
MachXO Family Data
ispDOWNLOAD Cable Data Sheet
V
TDO
TDI
NC
NC
TMS
TCK
NC
NC
Sheet. The TCK pin does not have a pull-up. A pull-down on the PCB of 4.7 K is
CCIO
Sheet. Valid voltage levels are 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V,
4.7K
V
12-3
CCIO
TDO
TDI
TMS
TCK
V
CCIO
for additional details.
MachXO
CC
CCIO.
MachXO JTAG Programming and
ramps up.
CCIO
To determine which bank contains the
®
pin. Any
Configuration User’s Guide
Cable connected to the download
®
or Lattice Diamond™ design
ispDOWNLOAD Cable Data
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