CAT28C256H13I-15 CATALYST SEMICONDUCTOR, CAT28C256H13I-15 Datasheet - Page 6

• Manufacturer Part Number: CAT28C256H13I-15
• Description: IC, EEPROM, 256KBIT, PARALLEL, TSOP-28
• Manufacturer: CATALYST SEMICONDUCTOR

Specifications of CAT28C256H13I-15

• Memory Size: 256Kbit
• Memory Configuration: 32K X 8
• Ic Interface Type: Parallel
• Access Time: 150ns
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: TSOP
• No. Of Pins: 28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DEVICE OPERATION
Read
bus when WE is held high, and both OE and CE are held low.
The data bus is set to a high impedance state when either CE
or OE goes high. This 2−line control architecture can be used
to eliminate bus contention in a system environment.
DATA OUT
ADDRESS
Data stored in the CAT28C256 is transferred to the data
DATA IN
WE
OE
CE
DATA OUT
ADDRESS
WE
OE
CE
V
t
AS
IH
t
OES
HIGH−Z
Figure 5. Byte Write Cycle [WE Controlled]
t
CS
t
t
AH
LZ
t
RC
t
CE
t
Figure 4. Read Cycle
OLZ
t
WP
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t
t
OE
DATA VALID
DS
HIGH−Z
6
DATA VALID
Byte Write
and OE is high. Write cycles can be initiated using either WE
or CE, with the address input being latched on the falling
edge of WE or CE, whichever occurs last. Data, conversely,
is latched on the rising edge of WE or CE, whichever occurs
first. Once initiated, a byte write cycle automatically erases
the addressed byte and the new data is written within 5 ms.
A write cycle is executed when both CE and WE are low,
t
OH
t
t
DH
CH
t
OEH
t
BLC
t
AA
t
WC
DATA VALID
t
t
OHZ
HZ